252 Commits

Author	SHA1	Message	Date
Wesley W. Terpstra	03bca77b33	tilelink2 Metadata: cannot assert data good when !valid	2016-11-18 17:16:12 -08:00
Wesley W. Terpstra	37a3c22639	rocketchip: move from using cde to config	2016-11-18 16:18:33 -08:00
Henry Cook	94086f2270	[tl2] broadcast hub probe port width bugfix	2016-11-17 18:42:59 -08:00
Henry Cook	960c2723ab	[tl2] MemoryOpCategories: use def to supply Cat'd consts	2016-11-17 18:42:59 -08:00
Wesley W. Terpstra	dfc3a0dafb	tilelink2: do not depend on obsolete TL1 configuration	2016-11-17 14:07:53 -08:00
Henry Cook	24e3216fcf	coreplex: allow zero interrupt sink/sources	2016-11-16 16:50:36 -08:00
Henry Cook	479bc82f03	tilelink2 Broadcast: improve bufferless throughput	2016-11-16 16:50:36 -08:00
Henry Cook	1f51564577	[rocket] dcache probe ack data bugfix	2016-11-16 14:25:21 -08:00
Wesley W. Terpstra	5d2e637a4a	tilelink2 Legacy: uncached TL never needs manager_xact_id	2016-11-16 12:16:25 -08:00
Wesley W. Terpstra	10e459fedb	rocket: change connection between rocketchip and coreplex ... * rtc and dtm are now crossed half-and-half on the two sides * groundtest no longer uses riscv platform traits	2016-11-15 18:27:52 -08:00
Wesley W. Terpstra	ab3dafb8bc	Monitor: restore Probe&Acquire checks	2016-11-14 15:36:52 -08:00
Henry Cook	c0efd247b0	[tl2] expand firstlast api and L1WB bugfix	2016-11-14 12:12:31 -08:00
Henry Cook	b7730d66f2	WIP bugfixes: run until corrupted WB data (beats repeated)	2016-11-11 18:34:48 -08:00
Henry Cook	afa1a6d549	WIP uncore and rocket changes compile	2016-11-10 15:57:29 -08:00
Wesley W. Terpstra	9d77e34bee	tilelink2 Filter: make transfer cap robust against large filters	2016-11-04 13:35:36 -07:00
Wesley W. Terpstra	b8df59f43b	tilelink2 Broadcast: support "bufferless" implementation	2016-11-04 13:35:36 -07:00
Wesley W. Terpstra	14800f8fb4	tilelink2 Broadcast: only support caching readable devices	2016-11-04 13:35:36 -07:00
Wesley W. Terpstra	0f3947bb86	tilelink2 Broadcast: add special case handling for 0 cached clients	2016-11-03 22:18:28 -07:00
Wesley W. Terpstra	ba3c83287f	tilelink2 Xbar: merge the AddressSets of fractured managers	2016-11-03 22:18:28 -07:00
Wesley W. Terpstra	55326c29bb	tilelink2: Filter adapter removes some of the address space	2016-11-03 22:18:23 -07:00
Wesley W. Terpstra	86ba94781b	tilelink2: broadcast coherence manager	2016-11-03 14:37:19 -07:00
Wesley W. Terpstra	d067e87a7d	tilelink2 Parameters: sinkId is per port, not per manager	2016-11-03 14:37:17 -07:00
Wesley W. Terpstra	ed4224dde4	tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull ... If we send out the PutFull portion of an AMO, the slave is allowed to respond with AccessAck on the same cycle. In this case, we are still in the AMO state, but must still match the D response.	2016-10-31 15:17:10 -07:00
Wesley W. Terpstra	ba529c3716	rocketchip: use TileLink2 interrupts	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	043ed48c8c	tilelink2 HintHandler: delay answers to help TL1 legacy clients	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	015c3b862a	diplomacy: print out bus widths on edges in agent graph	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	545154c1c3	groundtest: make it happy with TL2 addressing	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	9a26cb7ec7	Debug: mark the debug device executable	2016-10-31 11:42:47 -07:00
Wesley W. Terpstra	11121b6f4c	rocket: convert scratchpad to TL2	2016-10-31 11:42:13 -07:00
Wesley W. Terpstra	650f6fb23f	diplomacy: add BlindNodes for use as external ports	2016-10-31 11:41:18 -07:00
Wesley W. Terpstra	0edcd3304a	diplomacy Nodes: leave flipping to the MixedNode implementation	2016-10-31 11:41:18 -07:00
Andrew Waterman	e45b41b4b6	Don't rely on SeqMem output after read-enable is low	2016-10-27 23:44:10 -07:00
Wesley W. Terpstra	fee67c4abf	diplomacy: add methods to find {out,in}ner-most common node	2016-10-25 15:58:09 -07:00
Wesley W. Terpstra	4d50733548	tilelink2 ToAXI4: use helper method for a_last (#418)	2016-10-25 10:16:42 -07:00
Wesley W. Terpstra	4c815f7958	tilelink2 Parameters: fix {contains,supports}Safe (#416) ... When there is only one manager, you still want to know if the address was wrong on the link to that manager!	2016-10-24 20:37:04 -07:00
Wesley W. Terpstra	72e5a97d40	tilelink2: factor out the OH1ToOH function	2016-10-16 22:04:01 -07:00
Wesley W. Terpstra	20288729b9	tilelink2 Isolation: cross the valid signals as well ... Refactor the code to be less copy-pasty	2016-10-14 18:28:36 -07:00
Wesley W. Terpstra	ac0bb841da	AsyncQueue: cope with far reset propagation delay	2016-10-14 18:05:35 -07:00
Wesley W. Terpstra	8f3c2ddfc3	tilelink2 Crossing: these asserts should be done by the AsyncQueue	2016-10-14 16:54:09 -07:00
Wesley W. Terpstra	a82cfb8306	tilelink2: replace addr_hi with address (#397) ... When faced with ambiguous routing of wmask=0, we decided to include all the address bits. Hopefully in most cases the low bits will be optimized away anyway.	2016-10-14 14:09:39 -07:00
Wesley W. Terpstra	54b73aef57	tilelink2: WidthWidget and Fragmenter no longer erase latency	2016-10-13 17:02:18 -07:00
Wesley W. Terpstra	200cf3dd13	tilelink2 Nodes: include some options to test for conformance	2016-10-13 17:02:18 -07:00
Wesley W. Terpstra	5d5b5a66f4	tilelink2 RAMModel: fix a write-bad-data bug	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	e5a1483358	tilelink2 Fragmenter: eliminate most of the registers on A	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	99c7003d11	tilelink2: allow preemption of Fragmenter and WidthWidget	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	b42cfdc9dd	tilelink2 Arbiter: there is only one winner	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	b6e9b0c558	tilelink2 Arbiter: allow preemption of first beat	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	0aebf9e341	tilelink2 ToAXI4: no arbitration path register needed	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	0e897b905f	tilelink2 RegisterRouter: data path register is no longer required	2016-10-13 17:02:17 -07:00
Wesley W. Terpstra	c4eadd3ab3	tilelink2 Monitor: enforce stricter transaction ordering	2016-10-13 17:02:17 -07:00