Wesley W. Terpstra 20288729b9 tilelink2 Isolation: cross the valid signals as well ...

Refactor the code to be less copy-pasty

2016-10-14 18:28:36 -07:00

..

Arbiter.scala

tilelink2 Arbiter: there is only one winner

2016-10-13 17:02:17 -07:00

AtomicAutomata.scala

tilelink2 Arbiter: allow preemption of first beat

2016-10-13 17:02:17 -07:00

Buffer.scala

tilelink2: WidthWidget and Fragmenter no longer erase latency

2016-10-13 17:02:18 -07:00

Bundles.scala

AsyncQueue: cope with far reset propagation delay

2016-10-14 18:05:35 -07:00

Crossing.scala

tilelink2 Crossing: these asserts should be done by the AsyncQueue

2016-10-14 16:54:09 -07:00

Edges.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

Example.scala

tilelink2: move general-purpose code out of tilelink2 package

2016-10-03 16:22:28 -07:00

Fragmenter.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

Fuzzer.scala

tilelink2 RAMModel: include name of test in output

2016-10-12 17:08:52 -07:00

HintHandler.scala

tilelink2 Arbiter: allow preemption of first beat

2016-10-13 17:02:17 -07:00

IntNodes.scala

tilelink2: move general-purpose code out of tilelink2 package

2016-10-03 16:22:28 -07:00

Isolation.scala

tilelink2 Isolation: cross the valid signals as well

2016-10-14 18:28:36 -07:00

Legacy.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

Monitor.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

Nodes.scala

tilelink2 Nodes: include some options to test for conformance

2016-10-13 17:02:18 -07:00

package.scala

tilelink2: add a rightOR to go with our leftOR

2016-10-11 22:38:02 -07:00

Parameters.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

RAMModel.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

RegisterRouter.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

RegisterRouterTest.scala

regmapper: eliminate race condition in RegisterCrossing bypass

2016-10-10 13:13:32 -07:00

Repeater.scala

tilelink2 Fragmenter: eliminate most of the registers on A

2016-10-13 17:02:17 -07:00

SRAM.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

ToAXI4.scala

tilelink2 ToAXI4: no arbitration path register needed

2016-10-13 17:02:17 -07:00

WidthWidget.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

Xbar.scala

tilelink2 Arbiter: allow preemption of first beat

2016-10-13 17:02:17 -07:00