Wesley W. Terpstra b8df59f43b tilelink2 Broadcast: support "bufferless" implementation

2016-11-04 13:35:36 -07:00

..

Arbiter.scala

tilelink2 Arbiter: there is only one winner

2016-10-13 17:02:17 -07:00

AtomicAutomata.scala

tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull

2016-10-31 15:17:10 -07:00

Broadcast.scala

tilelink2 Broadcast: support "bufferless" implementation

2016-11-04 13:35:36 -07:00

Buffer.scala

tilelink2: WidthWidget and Fragmenter no longer erase latency

2016-10-13 17:02:18 -07:00

Bundles.scala

tilelink2: broadcast coherence manager

2016-11-03 14:37:19 -07:00

Crossing.scala

tilelink2 Crossing: these asserts should be done by the AsyncQueue

2016-10-14 16:54:09 -07:00

Edges.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

Example.scala

tilelink2: move general-purpose code out of tilelink2 package

2016-10-03 16:22:28 -07:00

Filter.scala

tilelink2: Filter adapter removes some of the address space

2016-11-03 22:18:23 -07:00

Fragmenter.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

Fuzzer.scala

tilelink2 RAMModel: include name of test in output

2016-10-12 17:08:52 -07:00

HintHandler.scala

tilelink2 Parameters: sinkId is per port, not per manager

2016-11-03 14:37:17 -07:00

IntNodes.scala

rocketchip: use TileLink2 interrupts

2016-10-31 11:42:47 -07:00

Isolation.scala

tilelink2 Isolation: cross the valid signals as well

2016-10-14 18:28:36 -07:00

Legacy.scala

groundtest: make it happy with TL2 addressing

2016-10-31 11:42:47 -07:00

Monitor.scala

tilelink2 Parameters: sinkId is per port, not per manager

2016-11-03 14:37:17 -07:00

Nodes.scala

tilelink2 Parameters: sinkId is per port, not per manager

2016-11-03 14:37:17 -07:00

package.scala

rocket: convert scratchpad to TL2

2016-10-31 11:42:13 -07:00

Parameters.scala

tilelink2 Xbar: merge the AddressSets of fractured managers

2016-11-03 22:18:28 -07:00

RAMModel.scala

tilelink2 Parameters: sinkId is per port, not per manager

2016-11-03 14:37:17 -07:00

RegisterRouter.scala

rocketchip: use TileLink2 interrupts

2016-10-31 11:42:47 -07:00

RegisterRouterTest.scala

regmapper: eliminate race condition in RegisterCrossing bypass

2016-10-10 13:13:32 -07:00

Repeater.scala

tilelink2 Fragmenter: eliminate most of the registers on A

2016-10-13 17:02:17 -07:00

SRAM.scala

Don't rely on SeqMem output after read-enable is low

2016-10-27 23:44:10 -07:00

ToAXI4.scala

tilelink2 Parameters: sinkId is per port, not per manager

2016-11-03 14:37:17 -07:00

WidthWidget.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

Xbar.scala

tilelink2 Xbar: merge the AddressSets of fractured managers

2016-11-03 22:18:28 -07:00