Wesley W. Terpstra 03bca77b33 tilelink2 Metadata: cannot assert data good when !valid

2016-11-18 17:16:12 -08:00

..

Arbiter.scala

tilelink2 Arbiter: there is only one winner

2016-10-13 17:02:17 -07:00

AtomicAutomata.scala

tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull

2016-10-31 15:17:10 -07:00

Broadcast.scala

[tl2] broadcast hub probe port width bugfix

2016-11-17 18:42:59 -08:00

Buffer.scala

tilelink2: WidthWidget and Fragmenter no longer erase latency

2016-10-13 17:02:18 -07:00

Bundles.scala

rocket: change connection between rocketchip and coreplex

2016-11-15 18:27:52 -08:00

Crossing.scala

tilelink2 Crossing: these asserts should be done by the AsyncQueue

2016-10-14 16:54:09 -07:00

Edges.scala

[tl2] expand firstlast api and L1WB bugfix

2016-11-14 12:12:31 -08:00

Example.scala

tilelink2: move general-purpose code out of tilelink2 package

2016-10-03 16:22:28 -07:00

Filter.scala

tilelink2 Filter: make transfer cap robust against large filters

2016-11-04 13:35:36 -07:00

Fragmenter.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

Fuzzer.scala

[tl2] expand firstlast api and L1WB bugfix

2016-11-14 12:12:31 -08:00

HintHandler.scala

tilelink2 Parameters: sinkId is per port, not per manager

2016-11-03 14:37:17 -07:00

IntNodes.scala

coreplex: allow zero interrupt sink/sources

2016-11-16 16:50:36 -08:00

Isolation.scala

rocket: change connection between rocketchip and coreplex

2016-11-15 18:27:52 -08:00

Legacy.scala

rocketchip: move from using cde to config

2016-11-18 16:18:33 -08:00

Metadata.scala

tilelink2 Metadata: cannot assert data good when !valid

2016-11-18 17:16:12 -08:00

Monitor.scala

Monitor: restore Probe&Acquire checks

2016-11-14 15:36:52 -08:00

Nodes.scala

tilelink2 Parameters: sinkId is per port, not per manager

2016-11-03 14:37:17 -07:00

package.scala

rocket: convert scratchpad to TL2

2016-10-31 11:42:13 -07:00

Parameters.scala

tilelink2 Xbar: merge the AddressSets of fractured managers

2016-11-03 22:18:28 -07:00

RAMModel.scala

[tl2] expand firstlast api and L1WB bugfix

2016-11-14 12:12:31 -08:00

RegisterRouter.scala

rocketchip: use TileLink2 interrupts

2016-10-31 11:42:47 -07:00

RegisterRouterTest.scala

regmapper: eliminate race condition in RegisterCrossing bypass

2016-10-10 13:13:32 -07:00

Repeater.scala

tilelink2 Fragmenter: eliminate most of the registers on A

2016-10-13 17:02:17 -07:00

SRAM.scala

Don't rely on SeqMem output after read-enable is low

2016-10-27 23:44:10 -07:00

ToAXI4.scala

[tl2] expand firstlast api and L1WB bugfix

2016-11-14 12:12:31 -08:00

WidthWidget.scala

tilelink2: replace addr_hi with address (#397)

2016-10-14 14:09:39 -07:00

Xbar.scala

tilelink2: do not depend on obsolete TL1 configuration

2016-11-17 14:07:53 -08:00