| .. |
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Arbiter.scala
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tilelink2 Arbiter: there is only one winner
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2016-10-13 17:02:17 -07:00 |
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AtomicAutomata.scala
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tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull
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2016-10-31 15:17:10 -07:00 |
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Broadcast.scala
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[tl2] broadcast hub probe port width bugfix
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2016-11-17 18:42:59 -08:00 |
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Buffer.scala
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tilelink2: WidthWidget and Fragmenter no longer erase latency
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2016-10-13 17:02:18 -07:00 |
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Bundles.scala
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rocket: change connection between rocketchip and coreplex
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2016-11-15 18:27:52 -08:00 |
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Crossing.scala
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tilelink2 Crossing: these asserts should be done by the AsyncQueue
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2016-10-14 16:54:09 -07:00 |
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Edges.scala
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[tl2] expand firstlast api and L1WB bugfix
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2016-11-14 12:12:31 -08:00 |
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Example.scala
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tilelink2: move general-purpose code out of tilelink2 package
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2016-10-03 16:22:28 -07:00 |
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Filter.scala
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tilelink2 Filter: make transfer cap robust against large filters
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2016-11-04 13:35:36 -07:00 |
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Fragmenter.scala
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tilelink2: replace addr_hi with address (#397)
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2016-10-14 14:09:39 -07:00 |
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Fuzzer.scala
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[tl2] expand firstlast api and L1WB bugfix
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2016-11-14 12:12:31 -08:00 |
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HintHandler.scala
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tilelink2 Parameters: sinkId is per port, not per manager
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2016-11-03 14:37:17 -07:00 |
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IntNodes.scala
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coreplex: allow zero interrupt sink/sources
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2016-11-16 16:50:36 -08:00 |
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Isolation.scala
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rocket: change connection between rocketchip and coreplex
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2016-11-15 18:27:52 -08:00 |
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Legacy.scala
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rocketchip: move from using cde to config
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2016-11-18 16:18:33 -08:00 |
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Metadata.scala
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tilelink2 Metadata: cannot assert data good when !valid
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2016-11-18 17:16:12 -08:00 |
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Monitor.scala
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Monitor: restore Probe&Acquire checks
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2016-11-14 15:36:52 -08:00 |
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Nodes.scala
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tilelink2 Parameters: sinkId is per port, not per manager
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2016-11-03 14:37:17 -07:00 |
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package.scala
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rocket: convert scratchpad to TL2
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2016-10-31 11:42:13 -07:00 |
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Parameters.scala
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tilelink2 Xbar: merge the AddressSets of fractured managers
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2016-11-03 22:18:28 -07:00 |
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RAMModel.scala
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[tl2] expand firstlast api and L1WB bugfix
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2016-11-14 12:12:31 -08:00 |
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RegisterRouter.scala
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rocketchip: use TileLink2 interrupts
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2016-10-31 11:42:47 -07:00 |
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RegisterRouterTest.scala
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regmapper: eliminate race condition in RegisterCrossing bypass
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2016-10-10 13:13:32 -07:00 |
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Repeater.scala
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tilelink2 Fragmenter: eliminate most of the registers on A
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2016-10-13 17:02:17 -07:00 |
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SRAM.scala
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Don't rely on SeqMem output after read-enable is low
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2016-10-27 23:44:10 -07:00 |
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ToAXI4.scala
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[tl2] expand firstlast api and L1WB bugfix
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2016-11-14 12:12:31 -08:00 |
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WidthWidget.scala
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tilelink2: replace addr_hi with address (#397)
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2016-10-14 14:09:39 -07:00 |
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Xbar.scala
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tilelink2: do not depend on obsolete TL1 configuration
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2016-11-17 14:07:53 -08:00 |
