Andrew Waterman
83fa489cef
Stop using HTIF CSR port
...
The port itself is still present to keep other stuff compiling.
2016-05-02 14:40:52 -07:00
Andrew Waterman
84fd45fd77
Pass TLB flush signal to I$ explicitly
2016-04-22 15:20:17 -07:00
Howard Mao
b7527268bb
use address map instead of MMIOBase to find size of memory
2016-04-21 18:44:39 -07:00
Andrew Waterman
51e0870e23
Separate I$ and D$ interface signals that span clock cycles
...
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
2016-04-01 19:30:39 -07:00
Andrew Waterman
37b9051762
No need to validate npc if BTB is disabled
2016-04-01 15:54:57 -07:00
Andrew Waterman
7ae44d4905
Add RV32 support
2016-03-10 17:32:00 -08:00
Andrew Waterman
bc15e8649e
WIP on priv spec v1.9
2016-03-02 23:29:58 -08:00
Howard Mao
78579672d3
make mtvec configurable and writeable
2016-01-29 14:51:56 -08:00
Howard Mao
305185c034
send DMA requests through MMIO and get responses through CSRs
2016-01-29 14:51:56 -08:00
Howard Mao
d51c127646
fix deprecation warnings in rocket.scala
2016-01-13 22:08:06 -08:00
Howard Mao
e80340198a
use implicit parameters for ALU
2015-11-30 17:35:33 -08:00
Andrew Waterman
e203b8b378
Make ALU generic for zscale
2015-11-24 19:17:07 -08:00
Andrew Waterman
5294e94794
Remove CSR back pressure ability
...
We were using it for IPIs, but no longer need it.
2015-11-24 18:28:14 -08:00
Andrew Waterman
4616db4695
Make RegFile/ImmGen usable by zscale
2015-11-24 18:27:07 -08:00
Henry Cook
4f8468b60f
depend on external cde library
2015-10-21 18:19:23 -07:00
Henry Cook
1a1185be3f
Vectorize ROCC and Tile memory interfaces
2015-10-20 15:02:24 -07:00
Henry Cook
8173695800
added HasAddrMapParameters
2015-10-06 18:22:40 -07:00
Henry Cook
84576650b5
Removed all traces of params
2015-10-05 21:48:05 -07:00
Andrew Waterman
833909a2b5
Chisel3 compatibility fixes
2015-09-30 14:36:26 -07:00
Andrew Waterman
f8a7a80644
Make perf counters optional
2015-09-28 13:55:23 -07:00
Howard Mao
9eb988a4c6
make sure access to invalid physical address treated as exception
2015-09-22 10:11:43 -07:00
Howard Mao
16c748576a
don't mux data_word_bypass between IOMSHR and cache
2015-09-22 10:10:57 -07:00
Christopher Celio
76bf1da310
[commitlog] zero-extend SP write-back values
2015-09-15 16:47:26 -07:00
Scott Beamer
3b48d8569c
[commitlog] don't print out writebacks to x0
2015-09-15 16:47:26 -07:00
Christopher Celio
7d14abf262
[commitlog] Added privilege-level to output
2015-09-15 16:47:24 -07:00
Christopher Celio
d630a03857
[commitlog] Added FP instructions to the commitlog
2015-09-15 15:59:13 -07:00
Christopher Celio
91458bef1c
[commitlog] Initial commit log for integer working
2015-09-15 15:59:03 -07:00
Andrew Waterman
78b2e947de
Chisel3 compatibility fixes
2015-09-11 15:43:07 -07:00
Andrew Waterman
546205b174
Chisel3 compatibility: use >>Int instead of >>UInt
2015-08-05 15:29:03 -07:00
Andrew Waterman
ef319edc84
Bits -> UInt
2015-08-02 21:03:42 -07:00
Andrew Waterman
52fc34a138
Chisel3: bulk connect is not commutative
...
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:11:25 -07:00
Andrew Waterman
6c0e1e33ab
Purge UInt := SInt assignments
2015-07-31 15:42:10 -07:00
Henry Cook
d2a594fb57
new junctions repo has mem size constants
2015-07-29 18:05:54 -07:00
Andrew Waterman
431dd2219b
Another Bits -> BitPat
2015-07-28 20:13:56 -07:00
Andrew Waterman
049fc8dc24
Chisel3 compatibility: use BitPat for don't-cares
...
This one's hella ugly, but for the time being, idgaf.
2015-07-28 02:48:49 -07:00
Andrew Waterman
e9433ee01e
Minor cleanup
2015-07-22 17:38:08 -07:00
Andrew Waterman
b4e4ceed3d
Factor out some more hazard detection code
2015-07-22 15:52:13 -07:00
Andrew Waterman
bd785e7d19
Factor out common hazard detection code
2015-07-22 15:46:20 -07:00
Andrew Waterman
cc447c8110
Refactor pipeline RTL (merge ctrl + dpath into rocket)
2015-07-21 17:10:56 -07:00
