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rocket-chip/src/main/scala/rocket/PTW.scala

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// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
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package freechips.rocketchip.rocket
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import Chisel._
Heterogeneous Tiles (#550) Fundamental new features: * Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces. * Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile. * Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile. * Defined RocketCoreParams: All the parameters that can be varied per-core. * Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes. * Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created. * Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little. * Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support. Additional changes that got rolled in along the way: * rocket: Fix critical path through BTB for I$ index bits > pgIdxBits * coreplex: tiles connected via :=* * groundtest: updated to use TileParams * tilelink: cache cork requirements are relaxed to allow more cacheless masters
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import Chisel.ImplicitConversions._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
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import freechips.rocketchip.util.property._
import chisel3.internal.sourceinfo.SourceInfo
import scala.collection.mutable.ListBuffer
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class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {
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val addr = UInt(width = vpnBits)
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}
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class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
val ae = Bool()
val pte = new PTE
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val level = UInt(width = log2Ceil(pgLevels))
val homogeneous = Bool()
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}
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class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
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val req = Decoupled(new PTWReq)
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val resp = Valid(new PTWResp).flip
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val ptbr = new PTBR().asInput
val status = new MStatus().asInput
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val pmp = Vec(nPMPs, new PMP).asInput
}
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class PTWPerfEvents extends Bundle {
val l2miss = Bool()
}
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class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
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val ptbr = new PTBR().asInput
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val sfence = Valid(new SFenceReq).flip
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val status = new MStatus().asInput
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val pmp = Vec(nPMPs, new PMP).asInput
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val perf = new PTWPerfEvents().asOutput
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}
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class PTE(implicit p: Parameters) extends CoreBundle()(p) {
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val ppn = UInt(width = 54)
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val reserved_for_software = Bits(width = 2)
val d = Bool()
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val a = Bool()
val g = Bool()
val u = Bool()
val x = Bool()
val w = Bool()
val r = Bool()
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val v = Bool()
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def table(dummy: Int = 0) = v && !r && !w && !x
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def leaf(dummy: Int = 0) = v && (r || (x && !w)) && a
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def ur(dummy: Int = 0) = sr() && u
def uw(dummy: Int = 0) = sw() && u
def ux(dummy: Int = 0) = sx() && u
def sr(dummy: Int = 0) = leaf() && r
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def sw(dummy: Int = 0) = leaf() && w && d
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def sx(dummy: Int = 0) = leaf() && x
}
class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
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val requestor = Vec(n, new TLBPTWIO).flip
val mem = new HellaCacheIO
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val dpath = new DatapathPTWIO
}
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val s_ready :: s_req :: s_wait1 :: s_wait2 :: Nil = Enum(UInt(), 4)
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val state = Reg(init=s_ready)
val count = Reg(UInt(width = log2Up(pgLevels)))
val s1_kill = Reg(next = Bool(false))
val resp_valid = Reg(next = Vec.fill(io.requestor.size)(Bool(false)))
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val resp_ae = Reg(Bool())
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val r_req = Reg(new PTWReq)
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val r_req_dest = Reg(Bits())
val r_pte = Reg(new PTE)
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val arb = Module(new RRArbiter(new PTWReq, n))
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arb.io.in <> io.requestor.map(_.req)
arb.io.out.ready := state === s_ready
val (pte, invalid_paddr) = {
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val tmp = new PTE().fromBits(io.mem.resp.bits.data)
val res = Wire(init = new PTE().fromBits(io.mem.resp.bits.data))
res.ppn := tmp.ppn(ppnBits-1, 0)
when (tmp.r || tmp.w || tmp.x) {
// for superpage mappings, make sure PPN LSBs are zero
for (i <- 0 until pgLevels-1)
when (count <= i && tmp.ppn((pgLevels-1-i)*pgLevelBits-1, (pgLevels-2-i)*pgLevelBits) =/= 0) { res.v := false }
}
(res, (tmp.ppn >> ppnBits) =/= 0)
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}
val traverse = pte.table() && !invalid_paddr && count < pgLevels-1
val pte_addr = if (!usingVM) 0.U else {
val vpn_idxs = (0 until pgLevels).map(i => (r_req.addr >> (pgLevels-i-1)*pgLevelBits)(pgLevelBits-1,0))
val vpn_idx = vpn_idxs(count)
Cat(r_pte.ppn, vpn_idx) << log2Ceil(xLen/8)
}
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when (arb.io.out.fire()) {
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r_req := arb.io.out.bits
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r_req_dest := arb.io.chosen
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r_pte.ppn := io.dpath.ptbr.ppn
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}
val (pte_cache_hit, pte_cache_data) = {
val size = 1 << log2Up(pgLevels * 2)
val plru = new PseudoLRU(size)
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val valid = Reg(init = UInt(0, size))
val tags = Reg(Vec(size, UInt(width = paddrBits)))
val data = Reg(Vec(size, UInt(width = ppnBits)))
val hits = tags.map(_ === pte_addr).asUInt & valid
val hit = hits.orR
when (io.mem.resp.valid && traverse && !hit) {
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val r = Mux(valid.andR, plru.replace, PriorityEncoder(~valid))
valid := valid | UIntToOH(r)
tags(r) := pte_addr
data(r) := pte.ppn
}
when (hit && state === s_req) { plru.access(OHToUInt(hits)) }
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when (io.dpath.sfence.valid && !io.dpath.sfence.bits.rs1) { valid := 0 }
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for (i <- 0 until pgLevels-1)
ccover(hit && state === s_req && count === i, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i")
(hit && count < pgLevels-1, Mux1H(hits, data))
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}
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val l2_refill = RegNext(false.B)
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io.dpath.perf.l2miss := false
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val (l2_hit, l2_valid, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, Wire(new PTE), None) else {
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val code = new ParityCode
require(isPow2(coreParams.nL2TLBEntries))
val idxBits = log2Ceil(coreParams.nL2TLBEntries)
val tagBits = vpnBits - idxBits
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class Entry extends Bundle {
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val tag = UInt(width = tagBits)
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val ppn = UInt(width = ppnBits)
val d = Bool()
val a = Bool()
val u = Bool()
val x = Bool()
val w = Bool()
val r = Bool()
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override def cloneType = new Entry().asInstanceOf[this.type]
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}
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val ram = SeqMem(coreParams.nL2TLBEntries, UInt(width = code.width(new Entry().getWidth)))
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val g = Reg(UInt(width = coreParams.nL2TLBEntries))
val valid = RegInit(UInt(0, coreParams.nL2TLBEntries))
val (r_tag, r_idx) = Split(r_req.addr, idxBits)
when (l2_refill) {
val entry = Wire(new Entry)
entry := r_pte
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entry.tag := r_tag
ram.write(r_idx, code.encode(entry.asUInt))
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val mask = UIntToOH(r_idx)
valid := valid | mask
g := Mux(r_pte.g, g | mask, g & ~mask)
}
when (io.dpath.sfence.valid) {
valid :=
Mux(io.dpath.sfence.bits.rs1, valid & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)),
Mux(io.dpath.sfence.bits.rs2, valid & g, 0.U))
}
val s0_valid = !l2_refill && arb.io.out.fire()
val s1_valid = RegNext(s0_valid)
val s2_valid = RegNext(s1_valid)
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val s1_rdata = ram.read(arb.io.out.bits.addr(idxBits-1, 0), s0_valid)
val s2_rdata = code.decode(RegEnable(s1_rdata, s1_valid))
val s2_valid_bit = RegEnable(valid(r_idx), s1_valid)
val s2_g = RegEnable(g(r_idx), s1_valid)
when (s2_valid && s2_valid_bit && s2_rdata.error) { valid := 0.U }
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val s2_entry = s2_rdata.uncorrected.asTypeOf(new Entry)
val s2_hit = s2_valid && s2_valid_bit && !s2_rdata.error && r_tag === s2_entry.tag
io.dpath.perf.l2miss := s2_valid && !(s2_valid_bit && r_tag === s2_entry.tag)
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val s2_pte = Wire(new PTE)
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s2_pte := s2_entry
s2_pte.g := s2_g
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s2_pte.v := true
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ccover(s2_hit, "L2_TLB_HIT", "L2 TLB hit")
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(s2_hit, s2_valid && s2_valid_bit, s2_pte, Some(ram))
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}
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io.mem.req.valid := state === s_req && !l2_valid
io.mem.req.bits.phys := Bool(true)
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io.mem.req.bits.cmd := M_XRD
io.mem.req.bits.typ := log2Ceil(xLen/8)
io.mem.req.bits.addr := pte_addr
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io.mem.s1_kill := s1_kill || l2_hit
io.mem.invalidate_lr := Bool(false)
val pmaPgLevelHomogeneous = (0 until pgLevels) map { i =>
TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) * pgLevelBits)))(pte_addr >> pgIdxBits << pgIdxBits).homogeneous
}
val pmaHomogeneous = pmaPgLevelHomogeneous(count)
val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(pte_addr >> pgIdxBits << pgIdxBits, count)
for (i <- 0 until io.requestor.size) {
io.requestor(i).resp.valid := resp_valid(i)
io.requestor(i).resp.bits.ae := resp_ae
io.requestor(i).resp.bits.pte := r_pte
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io.requestor(i).resp.bits.level := count
io.requestor(i).resp.bits.pte.ppn := pte_addr >> pgIdxBits
io.requestor(i).resp.bits.homogeneous := pmpHomogeneous && pmaHomogeneous
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io.requestor(i).ptbr := io.dpath.ptbr
io.requestor(i).status := io.dpath.status
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io.requestor(i).pmp := io.dpath.pmp
}
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// control state machine
switch (state) {
is (s_ready) {
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when (arb.io.out.fire()) {
state := s_req
}
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count := UInt(0)
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}
is (s_req) {
when (pte_cache_hit) {
s1_kill := true
count := count + 1
r_pte.ppn := pte_cache_data
}.elsewhen (io.mem.req.fire()) {
state := s_wait1
}
}
is (s_wait1) {
state := s_wait2
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}
is (s_wait2) {
when (io.mem.s2_nack) {
state := s_req
}
when (io.mem.resp.valid) {
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r_pte := pte
when (traverse) {
state := s_req
count := count + 1
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}.otherwise {
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l2_refill := pte.v && !invalid_paddr && count === pgLevels-1
resp_ae := pte.v && invalid_paddr
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state := s_ready
resp_valid(r_req_dest) := true
}
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}
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when (io.mem.s2_xcpt.ae.ld) {
resp_ae := true
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state := s_ready
resp_valid(r_req_dest) := true
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}
}
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}
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when (l2_hit) {
state := s_ready
resp_valid(r_req_dest) := true
resp_ae := false
r_pte := l2_pte
count := pgLevels-1
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}
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ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access")
ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table")
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def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
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if (usingVM) cover(cond, s"PTW_$label", "MemorySystem;;" + desc)
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}
/** Mix-ins for constructing tiles that might have a PTW */
trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile =>
val module: CanHavePTWModule
var nPTWPorts = 1
Heterogeneous Tiles (#550) Fundamental new features: * Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces. * Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile. * Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile. * Defined RocketCoreParams: All the parameters that can be varied per-core. * Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes. * Defined RocketTilesKey: A sequence of RocketTileParams, one for every tile to be created. * Provided HeterogeneousDualCoreConfig: An example of making a heterogeneous chip with two cores, one big and one little. * Changes to legacy code: ReplacementPolicy moved to package util. L1Metadata moved to package tile. Legacy L2 cache agent removed because it can no longer share the metadata array implementation with the L1. Legacy GroundTests on life support. Additional changes that got rolled in along the way: * rocket: Fix critical path through BTB for I$ index bits > pgIdxBits * coreplex: tiles connected via :=* * groundtest: updated to use TileParams * tilelink: cache cork requirements are relaxed to allow more cacheless masters
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nDCachePorts += usingPTW.toInt
}
trait CanHavePTWModule extends HasHellaCacheModule {
val outer: CanHavePTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
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val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
if (outer.usingPTW)
dcachePorts += ptw.io.mem
}