2014-09-13 00:31:38 +02:00
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// See LICENSE for license details.
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2014-04-23 01:55:35 +02:00
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package uncore
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import Chisel._
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2014-08-23 10:19:36 +02:00
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case object CacheName extends Field[String]
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2014-08-08 21:21:57 +02:00
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case object NSets extends Field[Int]
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case object NWays extends Field[Int]
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2014-08-12 03:35:49 +02:00
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case object BlockOffBits extends Field[Int]
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2014-08-08 21:21:57 +02:00
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case object RowBits extends Field[Int]
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case object WordBits extends Field[Int]
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case object Replacer extends Field[() => ReplacementPolicy]
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2014-05-07 10:51:46 +02:00
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2014-08-12 03:35:49 +02:00
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abstract trait CacheParameters extends UsesParameters {
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val paddrBits = params(PAddrBits)
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val vaddrBits = params(VAddrBits)
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val pgIdxBits = params(PgIdxBits)
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val nSets = params(NSets)
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val blockOffBits = params(BlockOffBits)
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val idxBits = log2Up(nSets)
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val untagBits = blockOffBits + idxBits
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val tagBits = paddrBits - untagBits
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2014-08-12 23:55:44 +02:00
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val nWays = params(NWays)
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2014-08-12 03:35:49 +02:00
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val wayBits = log2Up(nWays)
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val isDM = nWays == 1
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2014-08-12 23:55:44 +02:00
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val wordBits = params(WordBits)
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val wordBytes = wordBits/8
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val wordOffBits = log2Up(wordBytes)
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val rowBits = params(RowBits)
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2014-08-12 03:35:49 +02:00
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val rowWords = rowBits/wordBits
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2014-08-12 23:55:44 +02:00
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val rowBytes = rowBits/8
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2014-08-12 03:35:49 +02:00
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val rowOffBits = log2Up(rowBytes)
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}
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abstract class CacheBundle extends Bundle with CacheParameters
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abstract class CacheModule extends Module with CacheParameters
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2014-04-23 01:55:35 +02:00
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abstract class ReplacementPolicy {
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def way: UInt
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def miss: Unit
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def hit: Unit
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}
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2014-08-08 21:21:57 +02:00
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class RandomReplacement(ways: Int) extends ReplacementPolicy {
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2014-04-23 01:55:35 +02:00
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private val replace = Bool()
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replace := Bool(false)
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val lfsr = LFSR16(replace)
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2014-08-08 21:21:57 +02:00
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def way = if(ways == 1) UInt(0) else lfsr(log2Up(ways)-1,0)
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2014-04-23 01:55:35 +02:00
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def miss = replace := Bool(true)
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def hit = {}
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}
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2014-08-12 03:35:49 +02:00
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abstract class Metadata extends CacheBundle {
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val tag = Bits(width = tagBits)
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2014-05-28 22:35:08 +02:00
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val coh: CoherenceMetadata
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2014-04-23 01:55:35 +02:00
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}
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2014-08-12 03:35:49 +02:00
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class MetaReadReq extends CacheBundle {
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val idx = Bits(width = idxBits)
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2014-04-23 01:55:35 +02:00
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}
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2014-08-08 21:21:57 +02:00
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class MetaWriteReq[T <: Metadata](gen: T) extends MetaReadReq {
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2014-08-12 03:35:49 +02:00
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val way_en = Bits(width = nWays)
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2014-05-01 10:44:59 +02:00
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val data = gen.clone
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2014-08-08 21:21:57 +02:00
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override def clone = new MetaWriteReq(gen).asInstanceOf[this.type]
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2014-04-23 01:55:35 +02:00
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}
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2014-08-12 03:35:49 +02:00
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class MetadataArray[T <: Metadata](makeRstVal: () => T) extends CacheModule {
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2014-05-28 22:35:08 +02:00
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val rstVal = makeRstVal()
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2014-04-23 01:55:35 +02:00
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val io = new Bundle {
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2014-04-24 01:24:20 +02:00
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val read = Decoupled(new MetaReadReq).flip
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2014-05-06 21:59:45 +02:00
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val write = Decoupled(new MetaWriteReq(rstVal.clone)).flip
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2014-08-12 03:35:49 +02:00
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val resp = Vec.fill(nWays){rstVal.clone.asOutput}
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2014-04-23 01:55:35 +02:00
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}
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2014-05-06 21:59:45 +02:00
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val metabits = rstVal.getWidth
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2014-08-12 03:35:49 +02:00
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val rst_cnt = Reg(init=UInt(0, log2Up(nSets+1)))
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val rst = rst_cnt < UInt(nSets)
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2014-05-28 22:35:08 +02:00
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val waddr = Mux(rst, rst_cnt, io.write.bits.idx)
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val wdata = Mux(rst, rstVal, io.write.bits.data).toBits
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val wmask = Mux(rst, SInt(-1), io.write.bits.way_en)
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2014-04-23 01:55:35 +02:00
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when (rst) { rst_cnt := rst_cnt+UInt(1) }
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2014-08-12 03:35:49 +02:00
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val tag_arr = Mem(UInt(width = metabits*nWays), nSets, seqRead = true)
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2014-04-23 01:55:35 +02:00
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when (rst || io.write.valid) {
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2014-08-12 03:35:49 +02:00
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tag_arr.write(waddr, Fill(nWays, wdata), FillInterleaved(metabits, wmask))
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2014-04-23 01:55:35 +02:00
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}
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2014-05-28 22:35:08 +02:00
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val tags = tag_arr(RegEnable(io.read.bits.idx, io.read.valid))
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2014-08-12 03:35:49 +02:00
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for (w <- 0 until nWays) {
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2014-05-28 22:35:08 +02:00
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val m = tags(metabits*(w+1)-1, metabits*w)
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2014-05-06 21:59:45 +02:00
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io.resp(w) := rstVal.clone.fromBits(m)
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2014-04-23 01:55:35 +02:00
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}
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io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
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io.write.ready := !rst
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}
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2014-09-30 23:48:02 +02:00
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abstract trait L2HellaCacheParameters extends CacheParameters
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2014-12-17 23:28:14 +01:00
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with CoherenceAgentParameters {
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val idxMSB = idxBits-1
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val idxLSB = 0
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val refillCyclesPerBeat = params(TLDataBits)/rowBits
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val refillCycles = refillCyclesPerBeat*params(TLDataBeats)
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}
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2014-09-30 23:48:02 +02:00
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abstract class L2HellaCacheBundle extends Bundle with L2HellaCacheParameters
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abstract class L2HellaCacheModule extends Module with L2HellaCacheParameters
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trait HasL2Id extends Bundle with CoherenceAgentParameters {
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2014-12-19 12:03:53 +01:00
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val id = UInt(width = log2Up(nTransactors + 1))
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2014-09-30 23:48:02 +02:00
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}
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trait HasL2InternalRequestState extends L2HellaCacheBundle {
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val tag_match = Bool()
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val meta = new L2Metadata
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val way_en = Bits(width = nWays)
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}
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object L2Metadata {
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2014-12-30 07:55:58 +01:00
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def apply(tag: Bits, coh: ManagerMetadata) = {
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2014-09-30 23:48:02 +02:00
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val meta = new L2Metadata
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meta.tag := tag
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meta.coh := coh
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meta
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}
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}
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class L2Metadata extends Metadata with L2HellaCacheParameters {
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2014-12-30 07:55:58 +01:00
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val coh = new ManagerMetadata
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2014-09-30 23:48:02 +02:00
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}
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class L2MetaReadReq extends MetaReadReq with HasL2Id {
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val tag = Bits(width = tagBits)
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}
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class L2MetaWriteReq extends MetaWriteReq[L2Metadata](new L2Metadata)
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2014-10-15 20:46:35 +02:00
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with HasL2Id {
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override def clone = new L2MetaWriteReq().asInstanceOf[this.type]
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}
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2014-12-12 10:11:08 +01:00
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2014-09-30 23:48:02 +02:00
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class L2MetaResp extends L2HellaCacheBundle
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with HasL2Id
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with HasL2InternalRequestState
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2014-11-20 00:55:25 +01:00
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trait HasL2MetaReadIO extends L2HellaCacheBundle {
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val read = Decoupled(new L2MetaReadReq)
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val resp = Valid(new L2MetaResp).flip
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}
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trait HasL2MetaWriteIO extends L2HellaCacheBundle {
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val write = Decoupled(new L2MetaWriteReq)
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}
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class L2MetaRWIO extends L2HellaCacheBundle with HasL2MetaReadIO with HasL2MetaWriteIO
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2014-09-30 23:48:02 +02:00
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class L2MetadataArray extends L2HellaCacheModule {
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2014-11-20 00:55:25 +01:00
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val io = new L2MetaRWIO().flip
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2014-09-30 23:48:02 +02:00
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2014-12-30 07:55:58 +01:00
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val meta = Module(new MetadataArray(() => L2Metadata(UInt(0), co.managerMetadataOnFlush)))
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2014-09-30 23:48:02 +02:00
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meta.io.read <> io.read
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meta.io.write <> io.write
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val s1_tag = RegEnable(io.read.bits.tag, io.read.valid)
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val s1_id = RegEnable(io.read.bits.id, io.read.valid)
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def wayMap[T <: Data](f: Int => T) = Vec((0 until nWays).map(f))
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2014-12-12 10:11:08 +01:00
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val s1_clk_en = Reg(next = io.read.fire())
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2014-09-30 23:48:02 +02:00
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val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === s1_tag)
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val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && co.isValid(meta.io.resp(w).coh)).toBits
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val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
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val s2_tag_match = s2_tag_match_way.orR
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val s2_hit_coh = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en)))
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val replacer = params(Replacer)()
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val s1_replaced_way_en = UIntToOH(replacer.way)
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val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
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val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) =>
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RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
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2014-10-24 06:50:03 +02:00
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when(!s2_tag_match) { replacer.miss }
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2014-09-30 23:48:02 +02:00
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io.resp.valid := Reg(next = s1_clk_en)
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io.resp.bits.id := RegEnable(s1_id, s1_clk_en)
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io.resp.bits.tag_match := s2_tag_match
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io.resp.bits.meta := Mux(s2_tag_match,
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L2Metadata(s2_repl_meta.tag, s2_hit_coh),
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s2_repl_meta)
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io.resp.bits.way_en := Mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en)
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}
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class L2DataReadReq extends L2HellaCacheBundle with HasL2Id {
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val way_en = Bits(width = nWays)
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2014-11-13 01:25:25 +01:00
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val addr = Bits(width = tlAddrBits)
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2014-09-30 23:48:02 +02:00
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}
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class L2DataWriteReq extends L2DataReadReq {
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2014-11-13 01:25:25 +01:00
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val wmask = Bits(width = tlWriteMaskBits)
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val data = Bits(width = tlDataBits)
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2014-09-30 23:48:02 +02:00
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}
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2014-11-13 01:25:25 +01:00
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class L2DataResp extends Bundle with HasL2Id with TileLinkParameters {
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val data = Bits(width = tlDataBits)
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2014-09-30 23:48:02 +02:00
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}
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2014-11-20 00:55:25 +01:00
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trait HasL2DataReadIO extends L2HellaCacheBundle {
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val read = Decoupled(new L2DataReadReq)
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val resp = Valid(new L2DataResp).flip
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}
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trait HasL2DataWriteIO extends L2HellaCacheBundle {
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val write = Decoupled(new L2DataWriteReq)
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}
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class L2DataRWIO extends L2HellaCacheBundle with HasL2DataReadIO with HasL2DataWriteIO
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2014-09-30 23:48:02 +02:00
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class L2DataArray extends L2HellaCacheModule {
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2014-11-20 00:55:25 +01:00
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val io = new L2DataRWIO().flip
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2014-09-30 23:48:02 +02:00
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2014-10-24 06:50:03 +02:00
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val wmask = FillInterleaved(8, io.write.bits.wmask)
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2015-01-26 00:37:04 +01:00
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val reg_raddr = Reg(UInt())
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val array = Mem(Bits(width=rowBits), nWays*nSets*refillCycles, seqRead = true)
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val waddr = Cat(OHToUInt(io.write.bits.way_en), io.write.bits.addr)
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val raddr = Cat(OHToUInt(io.read.bits.way_en), io.read.bits.addr)
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when (io.write.bits.way_en.orR && io.write.valid) {
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array.write(waddr, io.write.bits.data, wmask)
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}.elsewhen (io.read.bits.way_en.orR && io.read.valid) {
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reg_raddr := raddr
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2014-09-30 23:48:02 +02:00
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}
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2015-01-26 00:37:04 +01:00
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2014-12-12 10:11:08 +01:00
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io.resp.valid := ShiftRegister(io.read.fire(), 1)
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io.resp.bits.id := ShiftRegister(io.read.bits.id, 1)
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2015-01-26 00:37:04 +01:00
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io.resp.bits.data := array(reg_raddr)
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io.read.ready := !io.write.valid
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2014-09-30 23:48:02 +02:00
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io.write.ready := Bool(true)
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}
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class L2HellaCache(bankId: Int, innerId: String, outerId: String) extends
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CoherenceAgent(innerId, outerId) with L2HellaCacheParameters {
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require(isPow2(nSets))
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require(isPow2(nWays))
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val tshrfile = Module(new TSHRFile(bankId, innerId, outerId))
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val meta = Module(new L2MetadataArray)
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val data = Module(new L2DataArray)
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tshrfile.io.inner <> io.inner
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2014-11-20 00:55:25 +01:00
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tshrfile.io.meta <> meta.io
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tshrfile.io.data <> data.io
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2014-09-30 23:48:02 +02:00
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io.outer <> tshrfile.io.outer
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io.incoherent <> tshrfile.io.incoherent
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}
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class TSHRFile(bankId: Int, innerId: String, outerId: String) extends L2HellaCacheModule {
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val io = new Bundle {
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val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
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val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
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val incoherent = Vec.fill(nClients){Bool()}.asInput
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2014-11-20 00:55:25 +01:00
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val meta = new L2MetaRWIO
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val data = new L2DataRWIO
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2014-09-30 23:48:02 +02:00
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}
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// Wiring helper funcs
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2014-12-12 10:11:08 +01:00
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def doOutputArbitration[T <: Data](out: DecoupledIO[T],
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ins: Seq[DecoupledIO[T]],
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count: Int = 1,
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lock: T => Bool = (a: T) => Bool(true)) {
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val arb = Module(new LockingRRArbiter(out.bits.clone, ins.size, count, lock))
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2014-09-30 23:48:02 +02:00
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out <> arb.io.out
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arb.io.in zip ins map { case (a, in) => a <> in }
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}
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def doInputRouting[T <: HasL2Id](in: ValidIO[T], outs: Seq[ValidIO[T]]) {
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outs.map(_.bits := in.bits)
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2014-10-24 06:50:03 +02:00
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outs.zipWithIndex.map { case (o, i) => o.valid := in.valid && (UInt(i) === in.bits.id) }
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// Create TSHRs for outstanding transactions
|
|
|
|
val trackerList = (0 until nReleaseTransactors).map { id =>
|
|
|
|
Module(new L2VoluntaryReleaseTracker(id, bankId, innerId, outerId))
|
|
|
|
} ++ (nReleaseTransactors until nTransactors).map { id =>
|
|
|
|
Module(new L2AcquireTracker(id, bankId, innerId, outerId))
|
|
|
|
}
|
|
|
|
|
2014-12-19 12:03:53 +01:00
|
|
|
val wb = Module(new L2WritebackUnit(nTransactors, bankId, innerId, outerId))
|
|
|
|
doOutputArbitration(wb.io.wb.req, trackerList.map(_.io.wb.req))
|
|
|
|
doInputRouting(wb.io.wb.resp, trackerList.map(_.io.wb.resp))
|
|
|
|
|
2014-09-30 23:48:02 +02:00
|
|
|
// Propagate incoherence flags
|
2014-12-19 12:03:53 +01:00
|
|
|
(trackerList.map(_.io.tile_incoherent) :+ wb.io.tile_incoherent).map( _ := io.incoherent.toBits)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
|
|
|
// Handle acquire transaction initiation
|
|
|
|
val acquire = io.inner.acquire
|
|
|
|
val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
|
2014-12-19 12:03:53 +01:00
|
|
|
val acquireList = trackerList.map(_.io.inner.acquire)
|
2014-12-20 02:39:23 +01:00
|
|
|
val acquireMatchList = trackerList.map(_.io.has_acquire_match)
|
|
|
|
val any_acquire_matches = acquireMatchList.reduce(_||_)
|
|
|
|
val alloc_idx = Vec(alloc_arb.io.in.map(_.ready)).lastIndexWhere{b: Bool => b}
|
|
|
|
val match_idx = Vec(acquireMatchList).indexWhere{b: Bool => b}
|
|
|
|
val acquire_idx = Mux(any_acquire_matches, match_idx, alloc_idx)
|
|
|
|
acquireList.zip(alloc_arb.io.in).zipWithIndex.map { case((acq, arb), i) =>
|
2014-12-19 12:03:53 +01:00
|
|
|
arb.valid := acq.ready
|
|
|
|
acq.bits := acquire.bits
|
2014-12-20 02:39:23 +01:00
|
|
|
acq.valid := acquire.valid && (acquire_idx === UInt(i))
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-12-20 02:39:23 +01:00
|
|
|
val block_acquires = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
|
2014-12-19 12:03:53 +01:00
|
|
|
acquire.ready := acquireList.map(_.ready).reduce(_||_) && !block_acquires
|
2014-09-30 23:48:02 +02:00
|
|
|
alloc_arb.io.out.ready := acquire.valid && !block_acquires
|
|
|
|
|
2014-12-19 12:03:53 +01:00
|
|
|
// Wire releases from clients
|
2014-09-30 23:48:02 +02:00
|
|
|
val release = io.inner.release
|
2014-12-19 12:03:53 +01:00
|
|
|
val release_idx = Vec(trackerList.map(_.io.has_release_match) :+
|
|
|
|
wb.io.has_release_match).indexWhere{b: Bool => b}
|
|
|
|
val releaseList = trackerList.map(_.io.inner.release) :+ wb.io.inner.release
|
|
|
|
releaseList.zipWithIndex.map { case(r, i) =>
|
|
|
|
r.bits := release.bits
|
|
|
|
r.valid := release.valid && (release_idx === UInt(i))
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-12-19 12:03:53 +01:00
|
|
|
release.ready := Vec(releaseList.map(_.ready)).read(release_idx)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
2014-12-12 10:11:08 +01:00
|
|
|
// Wire finished transaction acks
|
2014-10-03 10:06:33 +02:00
|
|
|
val finish = io.inner.finish
|
2014-12-30 07:55:58 +01:00
|
|
|
val finish_idx = finish.bits.payload.manager_xact_id
|
2014-10-03 10:06:33 +02:00
|
|
|
trackerList.zipWithIndex.map { case (t, i) =>
|
|
|
|
t.io.inner.finish.valid := finish.valid && finish_idx === UInt(i)
|
|
|
|
}
|
|
|
|
trackerList.map(_.io.inner.finish.bits := finish.bits)
|
|
|
|
finish.ready := Vec(trackerList.map(_.io.inner.finish.ready)).read(finish_idx)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
2014-12-12 10:11:08 +01:00
|
|
|
// Wire probe requests to clients
|
2014-12-19 12:03:53 +01:00
|
|
|
doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe) :+ wb.io.inner.probe)
|
2014-12-12 10:11:08 +01:00
|
|
|
|
|
|
|
// Wire grant reply to initiating client
|
|
|
|
def hasData(m: LogicalNetworkIO[Grant]) = co.messageHasData(m.payload)
|
|
|
|
doOutputArbitration(io.inner.grant, trackerList.map(_.io.inner.grant), tlDataBeats, hasData _)
|
|
|
|
|
|
|
|
// Create an arbiter for the one memory port
|
2014-12-19 12:03:53 +01:00
|
|
|
val outerList = trackerList.map(_.io.outer) :+ wb.io.outer
|
|
|
|
val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(outerList.size),
|
2014-09-30 23:48:02 +02:00
|
|
|
{case TLId => outerId})
|
2014-12-19 12:03:53 +01:00
|
|
|
outerList zip outer_arb.io.in map { case(out, arb) => out <> arb }
|
2014-09-30 23:48:02 +02:00
|
|
|
io.outer <> outer_arb.io.out
|
|
|
|
|
2014-12-12 10:11:08 +01:00
|
|
|
// Wire local memories
|
2014-11-20 00:55:25 +01:00
|
|
|
doOutputArbitration(io.meta.read, trackerList.map(_.io.meta.read))
|
|
|
|
doOutputArbitration(io.meta.write, trackerList.map(_.io.meta.write))
|
2014-12-19 12:03:53 +01:00
|
|
|
doOutputArbitration(io.data.read, trackerList.map(_.io.data.read) :+ wb.io.data.read, tlDataBeats)
|
|
|
|
doOutputArbitration(io.data.write, trackerList.map(_.io.data.write), tlDataBeats)
|
2014-11-20 00:55:25 +01:00
|
|
|
doInputRouting(io.meta.resp, trackerList.map(_.io.meta.resp))
|
2014-12-19 12:03:53 +01:00
|
|
|
doInputRouting(io.data.resp, trackerList.map(_.io.data.resp) :+ wb.io.data.resp)
|
|
|
|
}
|
|
|
|
|
|
|
|
class L2WritebackReq extends L2HellaCacheBundle
|
|
|
|
with HasL2Id {
|
|
|
|
val addr = UInt(width = tlAddrBits)
|
2014-12-30 07:55:58 +01:00
|
|
|
val coh = new ManagerMetadata
|
2014-12-19 12:03:53 +01:00
|
|
|
val way_en = Bits(width = nWays)
|
|
|
|
}
|
|
|
|
|
|
|
|
class L2WritebackResp extends L2HellaCacheBundle with HasL2Id
|
|
|
|
|
|
|
|
class L2WritebackIO extends L2HellaCacheBundle {
|
|
|
|
val req = Decoupled(new L2WritebackReq)
|
|
|
|
val resp = Valid(new L2WritebackResp).flip
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
|
2014-12-19 12:03:53 +01:00
|
|
|
class L2WritebackUnit(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2HellaCacheModule {
|
|
|
|
val io = new Bundle {
|
|
|
|
val wb = new L2WritebackIO().flip
|
|
|
|
val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
|
|
|
|
val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
|
|
|
|
val tile_incoherent = Bits(INPUT, nClients)
|
|
|
|
val has_release_match = Bool(OUTPUT)
|
|
|
|
val data = new L2DataRWIO
|
|
|
|
}
|
|
|
|
val c_acq = io.inner.acquire.bits
|
|
|
|
val c_rel = io.inner.release.bits
|
|
|
|
val c_gnt = io.inner.grant.bits
|
|
|
|
val c_ack = io.inner.finish.bits
|
|
|
|
val m_gnt = io.outer.grant.bits
|
|
|
|
|
|
|
|
val s_idle :: s_probe :: s_data_read :: s_data_resp :: s_outer_write :: Nil = Enum(UInt(), 5)
|
|
|
|
val state = Reg(init=s_idle)
|
|
|
|
|
|
|
|
val xact_addr = Reg(io.inner.acquire.bits.payload.addr.clone)
|
2014-12-30 07:55:58 +01:00
|
|
|
val xact_coh = Reg{ new ManagerMetadata }
|
2014-12-19 12:03:53 +01:00
|
|
|
val xact_way_en = Reg{ Bits(width = nWays) }
|
|
|
|
val xact_data = Vec.fill(tlDataBeats){ Reg(io.inner.acquire.bits.payload.data.clone) }
|
|
|
|
val xact_id = Reg{ UInt() }
|
|
|
|
|
|
|
|
val crel_had_data = Reg(init = Bool(false))
|
|
|
|
val release_count = Reg(init = UInt(0, width = log2Up(nClients+1)))
|
|
|
|
val pending_probes = Reg(init = co.dir.flush)
|
|
|
|
val curr_p_id = co.dir.next(pending_probes)
|
|
|
|
|
|
|
|
val (crel_data_cnt, crel_data_done) =
|
|
|
|
Counter(io.inner.release.fire() && co.messageHasData(io.inner.release.bits.payload), tlDataBeats)
|
|
|
|
val (outer_data_write_cnt, outer_data_write_done) =
|
|
|
|
Counter(io.outer.acquire.fire() && co.messageHasData(io.outer.acquire.bits.payload), tlDataBeats)
|
|
|
|
val (local_data_read_cnt, local_data_read_done) = Counter(io.data.read.fire(), tlDataBeats)
|
|
|
|
val (local_data_resp_cnt, local_data_resp_done) = Counter(io.data.resp.valid, tlDataBeats)
|
|
|
|
|
|
|
|
io.has_release_match := !co.isVoluntary(c_rel.payload) &&
|
|
|
|
co.isCoherenceConflict(xact_addr, c_rel.payload.addr) &&
|
|
|
|
(state === s_probe)
|
|
|
|
|
2014-12-30 07:55:58 +01:00
|
|
|
val next_coh_on_rel = co.managerMetadataOnRelease(c_rel.payload, xact_coh, c_rel.header.src)
|
2014-12-19 12:03:53 +01:00
|
|
|
|
|
|
|
io.outer.acquire.valid := Bool(false)
|
|
|
|
io.outer.acquire.bits.payload := Bundle(UncachedWrite(xact_addr,
|
|
|
|
UInt(trackerId),
|
|
|
|
xact_data(outer_data_write_cnt)),
|
|
|
|
{ case TLId => outerId })
|
|
|
|
io.outer.grant.ready := Bool(false) // Never gets mgnts
|
|
|
|
|
|
|
|
io.inner.probe.valid := Bool(false)
|
|
|
|
io.inner.probe.bits.header.src := UInt(bankId)
|
|
|
|
io.inner.probe.bits.header.dst := curr_p_id
|
|
|
|
io.inner.probe.bits.payload := Probe(co.getProbeTypeOnVoluntaryWriteback, xact_addr)
|
|
|
|
|
|
|
|
io.inner.grant.valid := Bool(false)
|
|
|
|
io.inner.acquire.ready := Bool(false)
|
|
|
|
io.inner.release.ready := Bool(false)
|
|
|
|
io.inner.finish.ready := Bool(false)
|
|
|
|
|
|
|
|
io.data.read.valid := Bool(false)
|
|
|
|
io.data.read.bits.id := UInt(trackerId)
|
|
|
|
io.data.read.bits.way_en := xact_way_en
|
|
|
|
io.data.read.bits.addr := Cat(xact_addr, local_data_read_cnt)
|
|
|
|
io.data.write.valid := Bool(false)
|
|
|
|
|
|
|
|
io.wb.req.ready := Bool(false)
|
|
|
|
io.wb.resp.valid := Bool(false)
|
|
|
|
io.wb.resp.bits.id := xact_id
|
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
is(s_idle) {
|
|
|
|
io.wb.req.ready := Bool(true)
|
|
|
|
when(io.wb.req.valid) {
|
|
|
|
xact_addr := io.wb.req.bits.addr
|
|
|
|
xact_coh := io.wb.req.bits.coh
|
|
|
|
xact_way_en := io.wb.req.bits.way_en
|
|
|
|
xact_id := io.wb.req.bits.id
|
|
|
|
val coh = io.wb.req.bits.coh
|
|
|
|
val needs_probes = co.requiresProbesOnVoluntaryWriteback(coh)
|
|
|
|
when(needs_probes) {
|
|
|
|
val mask_incoherent = co.dir.full(coh.sharers) & ~io.tile_incoherent
|
|
|
|
pending_probes := mask_incoherent
|
|
|
|
release_count := co.dir.count(mask_incoherent)
|
|
|
|
crel_had_data := Bool(false)
|
|
|
|
}
|
|
|
|
state := Mux(needs_probes, s_probe, s_data_read)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_probe) {
|
|
|
|
// Send probes
|
|
|
|
io.inner.probe.valid := !co.dir.none(pending_probes)
|
|
|
|
when(io.inner.probe.ready) {
|
|
|
|
pending_probes := co.dir.pop(pending_probes, curr_p_id)
|
|
|
|
}
|
|
|
|
// Handle releases, which may have data being written back
|
|
|
|
io.inner.release.ready := Bool(true)
|
|
|
|
when(io.inner.release.valid) {
|
|
|
|
xact_coh := next_coh_on_rel
|
|
|
|
// Handle released dirty data
|
|
|
|
when(co.messageHasData(c_rel.payload)) {
|
|
|
|
crel_had_data := Bool(true)
|
|
|
|
xact_data(crel_data_cnt) := c_rel.payload.data
|
|
|
|
}
|
|
|
|
// We don't decrement release_count until we've received all the data beats.
|
|
|
|
when(!co.messageHasData(c_rel.payload) || crel_data_done) {
|
|
|
|
release_count := release_count - UInt(1)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
when(release_count === UInt(0)) {
|
|
|
|
state := Mux(crel_had_data, s_outer_write, s_data_read)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_data_read) {
|
|
|
|
io.data.read.valid := Bool(true)
|
|
|
|
when(io.data.resp.valid) { xact_data(local_data_resp_cnt) := io.data.resp.bits.data }
|
|
|
|
when(local_data_read_done) { state := s_data_resp }
|
|
|
|
}
|
|
|
|
is(s_data_resp) {
|
|
|
|
when(io.data.resp.valid) { xact_data(local_data_resp_cnt) := io.data.resp.bits.data }
|
|
|
|
when(local_data_resp_done) { state := s_outer_write }
|
|
|
|
}
|
|
|
|
is(s_outer_write) {
|
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
when(outer_data_write_done) {
|
|
|
|
io.wb.resp.valid := Bool(true)
|
|
|
|
state := s_idle
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2014-09-30 23:48:02 +02:00
|
|
|
|
|
|
|
abstract class L2XactTracker(innerId: String, outerId: String) extends L2HellaCacheModule {
|
|
|
|
val io = new Bundle {
|
|
|
|
val inner = Bundle(new TileLinkIO, {case TLId => innerId}).flip
|
|
|
|
val outer = Bundle(new UncachedTileLinkIO, {case TLId => outerId})
|
|
|
|
val tile_incoherent = Bits(INPUT, nClients)
|
|
|
|
val has_acquire_conflict = Bool(OUTPUT)
|
2014-12-20 02:39:23 +01:00
|
|
|
val has_acquire_match = Bool(OUTPUT)
|
2014-12-19 02:12:29 +01:00
|
|
|
val has_release_match = Bool(OUTPUT)
|
2014-11-20 00:55:25 +01:00
|
|
|
val data = new L2DataRWIO
|
|
|
|
val meta = new L2MetaRWIO
|
2014-12-19 12:03:53 +01:00
|
|
|
val wb = new L2WritebackIO
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
val c_acq = io.inner.acquire.bits
|
|
|
|
val c_rel = io.inner.release.bits
|
|
|
|
val c_gnt = io.inner.grant.bits
|
|
|
|
val c_ack = io.inner.finish.bits
|
|
|
|
val m_gnt = io.outer.grant.bits
|
|
|
|
|
2014-12-12 10:11:08 +01:00
|
|
|
def mergeData(acq: Acquire, old_data: UInt, new_data: UInt): UInt = {
|
|
|
|
//TODO apply acq's write mask
|
|
|
|
Mux(co.messageHasData(acq), old_data, new_data)
|
2014-10-08 07:33:10 +02:00
|
|
|
}
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) {
|
2014-10-24 06:50:03 +02:00
|
|
|
val s_idle :: s_meta_read :: s_meta_resp :: s_data_write :: s_meta_write :: s_grant :: s_busy :: Nil = Enum(UInt(), 7)
|
2014-09-30 23:48:02 +02:00
|
|
|
val state = Reg(init=s_idle)
|
2014-12-12 10:11:08 +01:00
|
|
|
|
|
|
|
val xact_src = Reg(io.inner.release.bits.header.src.clone)
|
|
|
|
val xact_r_type = Reg(io.inner.release.bits.payload.r_type)
|
|
|
|
val xact_addr = Reg(io.inner.release.bits.payload.addr.clone)
|
|
|
|
val xact_client_xact_id = Reg(io.inner.release.bits.payload.client_xact_id.clone)
|
|
|
|
val xact_data = Vec.fill(tlDataBeats){ Reg(io.inner.release.bits.payload.data.clone) }
|
|
|
|
val xact_tag_match = Reg{ Bool() }
|
|
|
|
val xact_meta = Reg{ new L2Metadata }
|
|
|
|
val xact_way_en = Reg{ Bits(width = nWays) }
|
|
|
|
val xact = Release(xact_r_type, xact_addr, xact_client_xact_id)
|
|
|
|
|
|
|
|
val collect_inner_data = Reg(init=Bool(false))
|
|
|
|
val (inner_data_cnt, inner_data_done) =
|
|
|
|
Counter(io.inner.release.fire() && co.messageHasData(io.inner.release.bits.payload), tlDataBeats)
|
|
|
|
val (local_data_cnt, local_data_done) =
|
|
|
|
Counter(io.data.write.fire(), tlDataBeats)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
|
|
|
io.has_acquire_conflict := Bool(false)
|
2014-12-20 02:39:23 +01:00
|
|
|
io.has_acquire_match := Bool(false)
|
2014-12-19 02:12:29 +01:00
|
|
|
io.has_release_match := co.isVoluntary(c_rel.payload)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
|
|
|
io.outer.grant.ready := Bool(false)
|
|
|
|
io.outer.acquire.valid := Bool(false)
|
|
|
|
io.inner.acquire.ready := Bool(false)
|
|
|
|
io.inner.probe.valid := Bool(false)
|
|
|
|
io.inner.release.ready := Bool(false)
|
|
|
|
io.inner.grant.valid := Bool(false)
|
2014-10-24 06:50:03 +02:00
|
|
|
io.inner.finish.ready := Bool(false)
|
|
|
|
|
2014-09-30 23:48:02 +02:00
|
|
|
io.inner.grant.bits.header.src := UInt(bankId)
|
2014-12-12 10:11:08 +01:00
|
|
|
io.inner.grant.bits.header.dst := xact_src
|
2014-11-13 01:25:25 +01:00
|
|
|
io.inner.grant.bits.payload := Grant(Bool(false),
|
2014-12-12 10:11:08 +01:00
|
|
|
co.getGrantTypeOnVoluntaryWriteback(xact_meta.coh),
|
|
|
|
xact_client_xact_id,
|
2014-09-30 23:48:02 +02:00
|
|
|
UInt(trackerId))
|
|
|
|
|
2014-11-20 00:55:25 +01:00
|
|
|
io.data.read.valid := Bool(false)
|
|
|
|
io.data.write.valid := Bool(false)
|
|
|
|
io.data.write.bits.id := UInt(trackerId)
|
2014-12-12 10:11:08 +01:00
|
|
|
io.data.write.bits.way_en := xact_way_en
|
|
|
|
io.data.write.bits.addr := Cat(xact_addr, local_data_cnt)
|
2014-11-20 00:55:25 +01:00
|
|
|
io.data.write.bits.wmask := SInt(-1)
|
2014-12-12 10:11:08 +01:00
|
|
|
io.data.write.bits.data := xact_data(local_data_cnt)
|
2014-11-20 00:55:25 +01:00
|
|
|
io.meta.read.valid := Bool(false)
|
|
|
|
io.meta.read.bits.id := UInt(trackerId)
|
2014-12-17 23:28:14 +01:00
|
|
|
io.meta.read.bits.idx := xact_addr(idxMSB,idxLSB)
|
|
|
|
io.meta.read.bits.tag := xact_addr >> UInt(idxBits)
|
2014-11-20 00:55:25 +01:00
|
|
|
io.meta.write.valid := Bool(false)
|
|
|
|
io.meta.write.bits.id := UInt(trackerId)
|
2014-12-17 23:28:14 +01:00
|
|
|
io.meta.write.bits.idx := xact_addr(idxMSB,idxLSB)
|
2014-12-12 10:11:08 +01:00
|
|
|
io.meta.write.bits.way_en := xact_way_en
|
2014-12-17 23:28:14 +01:00
|
|
|
io.meta.write.bits.data.tag := xact_addr >> UInt(idxBits)
|
2014-12-30 07:55:58 +01:00
|
|
|
io.meta.write.bits.data.coh := co.managerMetadataOnRelease(xact,
|
2014-12-12 10:11:08 +01:00
|
|
|
xact_meta.coh,
|
|
|
|
xact_src)
|
2014-12-19 12:03:53 +01:00
|
|
|
io.wb.req.valid := Bool(false)
|
2014-12-12 10:11:08 +01:00
|
|
|
|
|
|
|
when(collect_inner_data) {
|
|
|
|
io.inner.release.ready := Bool(true)
|
|
|
|
when(io.inner.release.valid) {
|
|
|
|
xact_data(inner_data_cnt) := c_rel.payload.data
|
|
|
|
}
|
|
|
|
when(inner_data_done) { collect_inner_data := Bool(false) }
|
|
|
|
}
|
2014-09-30 23:48:02 +02:00
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
is(s_idle) {
|
|
|
|
io.inner.release.ready := Bool(true)
|
|
|
|
when( io.inner.release.valid ) {
|
2014-12-12 10:11:08 +01:00
|
|
|
xact_src := c_rel.header.src
|
|
|
|
xact_r_type := c_rel.payload.r_type
|
|
|
|
xact_addr := c_rel.payload.addr
|
|
|
|
xact_client_xact_id := c_rel.payload.client_xact_id
|
|
|
|
xact_data(UInt(0)) := c_rel.payload.data
|
|
|
|
collect_inner_data := co.messageHasData(c_rel.payload)
|
2014-10-03 10:06:33 +02:00
|
|
|
state := s_meta_read
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-10-03 10:06:33 +02:00
|
|
|
}
|
2014-09-30 23:48:02 +02:00
|
|
|
is(s_meta_read) {
|
2014-11-20 00:55:25 +01:00
|
|
|
io.meta.read.valid := Bool(true)
|
|
|
|
when(io.meta.read.ready) { state := s_meta_resp }
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
is(s_meta_resp) {
|
2014-11-20 00:55:25 +01:00
|
|
|
when(io.meta.resp.valid) {
|
2014-12-12 10:11:08 +01:00
|
|
|
xact_tag_match := io.meta.resp.bits.tag_match
|
|
|
|
xact_meta := io.meta.resp.bits.meta
|
|
|
|
xact_way_en := io.meta.resp.bits.way_en
|
2014-11-20 00:55:25 +01:00
|
|
|
state := Mux(io.meta.resp.bits.tag_match,
|
2014-10-08 07:33:10 +02:00
|
|
|
Mux(co.messageHasData(xact), s_data_write, s_meta_write),
|
|
|
|
s_grant)
|
2014-10-03 10:06:33 +02:00
|
|
|
}
|
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
is(s_data_write) {
|
2014-12-12 10:11:08 +01:00
|
|
|
io.data.write.valid := (if(tlDataBeats == 1) Bool(true)
|
|
|
|
else !collect_inner_data || (local_data_cnt < inner_data_cnt))
|
|
|
|
when(local_data_done) { state := s_meta_write }
|
2014-10-08 07:33:10 +02:00
|
|
|
}
|
2014-10-03 10:06:33 +02:00
|
|
|
is(s_meta_write) {
|
2014-11-20 00:55:25 +01:00
|
|
|
io.meta.write.valid := Bool(true)
|
|
|
|
when(io.meta.write.ready) { state := s_grant }
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
is(s_grant) {
|
2014-09-30 23:48:02 +02:00
|
|
|
io.inner.grant.valid := Bool(true)
|
2014-10-03 10:06:33 +02:00
|
|
|
when(io.inner.grant.ready) {
|
2014-11-13 01:25:25 +01:00
|
|
|
state := Mux(co.requiresAckForGrant(c_gnt.payload),
|
2014-10-03 10:06:33 +02:00
|
|
|
s_busy, s_idle)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_busy) {
|
2014-10-24 06:50:03 +02:00
|
|
|
io.inner.finish.ready := Bool(true)
|
2014-10-03 10:06:33 +02:00
|
|
|
when(io.inner.finish.valid) { state := s_idle }
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-12-19 12:03:53 +01:00
|
|
|
|
2014-09-30 23:48:02 +02:00
|
|
|
class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: String) extends L2XactTracker(innerId, outerId) {
|
2014-12-19 12:03:53 +01:00
|
|
|
val s_idle :: s_meta_read :: s_meta_resp :: s_wb_req :: s_wb_resp :: s_probe :: s_outer_read :: s_outer_resp :: s_data_read :: s_data_resp :: s_data_write :: s_meta_write :: s_grant :: s_busy :: Nil = Enum(UInt(), 14)
|
2014-09-30 23:48:02 +02:00
|
|
|
val state = Reg(init=s_idle)
|
2014-12-12 10:11:08 +01:00
|
|
|
|
|
|
|
val xact_src = Reg(io.inner.acquire.bits.header.src.clone)
|
|
|
|
val xact_uncached = Reg(io.inner.acquire.bits.payload.uncached.clone)
|
|
|
|
val xact_a_type = Reg(io.inner.acquire.bits.payload.a_type.clone)
|
|
|
|
val xact_addr = Reg(io.inner.acquire.bits.payload.addr.clone)
|
|
|
|
val xact_client_xact_id = Reg(io.inner.acquire.bits.payload.client_xact_id.clone)
|
|
|
|
val xact_subblock = Reg(io.inner.acquire.bits.payload.subblock.clone)
|
|
|
|
val xact_data = Vec.fill(tlDataBeats){ Reg(io.inner.acquire.bits.payload.data.clone) }
|
|
|
|
val xact_tag_match = Reg{ Bool() }
|
|
|
|
val xact_meta = Reg{ new L2Metadata }
|
|
|
|
val xact_way_en = Reg{ Bits(width = nWays) }
|
|
|
|
val xact = Acquire(xact_uncached, xact_a_type, xact_addr, xact_client_xact_id, UInt(0), xact_subblock)
|
|
|
|
|
2014-10-24 06:50:03 +02:00
|
|
|
val crel_had_data = Reg(init = Bool(false))
|
2014-12-19 12:03:53 +01:00
|
|
|
val release_count = Reg(init = UInt(0, width = log2Up(nClients+1)))
|
|
|
|
val pending_probes = Reg(init = UInt(0, width = nCoherentClients))
|
|
|
|
val curr_p_id = co.dir.next(pending_probes)
|
|
|
|
val full_sharers = co.dir.full(io.meta.resp.bits.meta.coh.sharers)
|
|
|
|
val mask_self = Mux(co.requiresSelfProbe(xact),
|
|
|
|
full_sharers | (UInt(1) << xact_src),
|
|
|
|
full_sharers & ~UInt(UInt(1) << xact_src, width = nClients))
|
|
|
|
val mask_incoherent = mask_self & ~io.tile_incoherent
|
2014-12-12 10:11:08 +01:00
|
|
|
|
|
|
|
val collect_cacq_data = Reg(init=Bool(false))
|
|
|
|
//TODO: zero width wires
|
2014-12-19 12:03:53 +01:00
|
|
|
val (cacq_data_cnt, cacq_data_done) =
|
2014-12-12 10:11:08 +01:00
|
|
|
Counter(io.inner.acquire.fire() && co.messageHasData(io.inner.acquire.bits.payload), tlDataBeats)
|
2014-12-19 12:03:53 +01:00
|
|
|
val (crel_data_cnt, crel_data_done) =
|
2014-12-12 10:11:08 +01:00
|
|
|
Counter(io.inner.release.fire() && co.messageHasData(io.inner.release.bits.payload), tlDataBeats)
|
2014-12-19 12:03:53 +01:00
|
|
|
val (cgnt_data_cnt, cgnt_data_done) =
|
2014-12-12 10:11:08 +01:00
|
|
|
Counter(io.inner.grant.fire() && co.messageHasData(io.inner.grant.bits.payload), tlDataBeats)
|
2014-12-19 12:03:53 +01:00
|
|
|
val (outer_data_write_cnt, outer_data_write_done) =
|
2014-12-12 10:11:08 +01:00
|
|
|
Counter(io.outer.acquire.fire() && co.messageHasData(io.outer.acquire.bits.payload), tlDataBeats)
|
2014-12-19 12:03:53 +01:00
|
|
|
val (outer_data_resp_cnt, outer_data_resp_done) =
|
2014-12-12 10:11:08 +01:00
|
|
|
Counter(io.outer.grant.fire() && co.messageHasData(io.outer.grant.bits.payload), tlDataBeats)
|
|
|
|
val (local_data_read_cnt, local_data_read_done) = Counter(io.data.read.fire(), tlDataBeats)
|
|
|
|
val (local_data_write_cnt, local_data_write_done) = Counter(io.data.write.fire(), tlDataBeats)
|
|
|
|
val (local_data_resp_cnt, local_data_resp_done) = Counter(io.data.resp.valid, tlDataBeats)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
2014-12-12 10:11:08 +01:00
|
|
|
val needs_writeback = !xact_tag_match && co.needsWriteback(xact_meta.coh)
|
|
|
|
val is_hit = xact_tag_match && co.isHit(xact, xact_meta.coh)
|
|
|
|
val needs_probes = co.requiresProbes(xact, xact_meta.coh)
|
|
|
|
//TODO: uncached does or does not allocate
|
|
|
|
|
|
|
|
//TODO: Are there any races between lines with the same idx?
|
|
|
|
//TODO: Allow hit under miss for stores
|
|
|
|
io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) &&
|
2014-12-17 23:28:14 +01:00
|
|
|
xact.addr(idxMSB,idxLSB) === c_acq.payload.addr(idxMSB,idxLSB) &&
|
2014-12-12 10:11:08 +01:00
|
|
|
(state != s_idle) &&
|
|
|
|
!collect_cacq_data
|
2014-12-20 02:39:23 +01:00
|
|
|
io.has_acquire_match := co.messageHasData(xact) &&
|
|
|
|
(xact.addr === c_acq.payload.addr) &&
|
|
|
|
collect_cacq_data
|
2014-12-19 02:12:29 +01:00
|
|
|
io.has_release_match := !co.isVoluntary(c_rel.payload) &&
|
2014-12-20 02:39:23 +01:00
|
|
|
(xact.addr === c_rel.payload.addr) &&
|
2014-12-19 02:12:29 +01:00
|
|
|
(state === s_probe)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
2014-12-30 07:55:58 +01:00
|
|
|
val next_coh_on_rel = co.managerMetadataOnRelease(c_rel.payload, xact_meta.coh, c_rel.header.src)
|
|
|
|
val next_coh_on_gnt = co.managerMetadataOnGrant(c_gnt.payload, xact_meta.coh,
|
2014-10-24 06:50:03 +02:00
|
|
|
c_gnt.header.dst)
|
|
|
|
|
2014-12-19 12:03:53 +01:00
|
|
|
val outer_write = Bundle(UncachedWrite(xact_addr, UInt(trackerId), xact_data(outer_data_write_cnt)),
|
2014-11-13 01:25:25 +01:00
|
|
|
{ case TLId => outerId })
|
2014-12-12 10:11:08 +01:00
|
|
|
val outer_read = Bundle(UncachedRead( xact_addr, UInt(trackerId)), { case TLId => outerId })
|
2014-11-13 01:25:25 +01:00
|
|
|
|
2014-09-30 23:48:02 +02:00
|
|
|
io.outer.acquire.valid := Bool(false)
|
2014-10-08 07:33:10 +02:00
|
|
|
io.outer.acquire.bits.payload := outer_read //default
|
|
|
|
io.outer.grant.ready := Bool(true) //grant.data -> xact.data
|
|
|
|
|
2014-09-30 23:48:02 +02:00
|
|
|
io.inner.probe.valid := Bool(false)
|
|
|
|
io.inner.probe.bits.header.src := UInt(bankId)
|
|
|
|
io.inner.probe.bits.header.dst := curr_p_id
|
2014-12-19 12:03:53 +01:00
|
|
|
io.inner.probe.bits.payload := Probe(co.getProbeType(xact, xact_meta.coh), xact_addr)
|
|
|
|
|
2014-09-30 23:48:02 +02:00
|
|
|
io.inner.grant.valid := Bool(false)
|
|
|
|
io.inner.grant.bits.header.src := UInt(bankId)
|
2014-12-19 12:03:53 +01:00
|
|
|
io.inner.grant.bits.header.dst := xact_src
|
|
|
|
io.inner.grant.bits.payload := Grant(xact_uncached, co.getGrantType(xact, xact_meta.coh),
|
|
|
|
xact_client_xact_id,
|
|
|
|
UInt(trackerId),
|
|
|
|
xact_data(cgnt_data_cnt))
|
2014-09-30 23:48:02 +02:00
|
|
|
|
|
|
|
io.inner.acquire.ready := Bool(false)
|
|
|
|
io.inner.release.ready := Bool(false)
|
2014-10-24 06:50:03 +02:00
|
|
|
io.inner.finish.ready := Bool(false)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
2014-11-20 00:55:25 +01:00
|
|
|
io.data.read.valid := Bool(false)
|
|
|
|
io.data.read.bits.id := UInt(trackerId)
|
2014-12-12 10:11:08 +01:00
|
|
|
io.data.read.bits.way_en := xact_way_en
|
|
|
|
io.data.read.bits.addr := Cat(xact_addr, local_data_read_cnt)
|
2014-11-20 00:55:25 +01:00
|
|
|
io.data.write.valid := Bool(false)
|
|
|
|
io.data.write.bits.id := UInt(trackerId)
|
2014-12-12 10:11:08 +01:00
|
|
|
io.data.write.bits.way_en := xact_way_en
|
|
|
|
io.data.write.bits.addr := Cat(xact_addr, local_data_write_cnt)
|
2014-11-20 00:55:25 +01:00
|
|
|
io.data.write.bits.wmask := SInt(-1)
|
2014-12-12 10:11:08 +01:00
|
|
|
io.data.write.bits.data := xact_data(local_data_write_cnt)
|
2014-11-20 00:55:25 +01:00
|
|
|
io.meta.read.valid := Bool(false)
|
|
|
|
io.meta.read.bits.id := UInt(trackerId)
|
2014-12-17 23:28:14 +01:00
|
|
|
io.meta.read.bits.idx := xact_addr(idxMSB,idxLSB)
|
|
|
|
io.meta.read.bits.tag := xact_addr >> UInt(idxBits)
|
2014-11-20 00:55:25 +01:00
|
|
|
io.meta.write.valid := Bool(false)
|
|
|
|
io.meta.write.bits.id := UInt(trackerId)
|
2014-12-17 23:28:14 +01:00
|
|
|
io.meta.write.bits.idx := xact_addr(idxMSB,idxLSB)
|
2014-12-12 10:11:08 +01:00
|
|
|
io.meta.write.bits.way_en := xact_way_en
|
2014-12-17 23:28:14 +01:00
|
|
|
io.meta.write.bits.data.tag := xact_addr >> UInt(idxBits)
|
2014-12-19 12:03:53 +01:00
|
|
|
io.meta.write.bits.data.coh := next_coh_on_gnt
|
|
|
|
|
|
|
|
io.wb.req.valid := Bool(false)
|
|
|
|
io.wb.req.bits.addr := Cat(xact_meta.tag, xact_addr(idxMSB,idxLSB))
|
|
|
|
io.wb.req.bits.coh := xact_meta.coh
|
|
|
|
io.wb.req.bits.way_en := xact_way_en
|
|
|
|
io.wb.req.bits.id := UInt(trackerId)
|
2014-09-30 23:48:02 +02:00
|
|
|
|
2014-12-12 10:11:08 +01:00
|
|
|
when(collect_cacq_data) {
|
|
|
|
io.inner.acquire.ready := Bool(true)
|
|
|
|
when(io.inner.acquire.valid) {
|
|
|
|
xact_data(cacq_data_cnt) := c_acq.payload.data
|
|
|
|
}
|
|
|
|
when(cacq_data_done) { collect_cacq_data := Bool(false) }
|
|
|
|
}
|
|
|
|
|
2014-09-30 23:48:02 +02:00
|
|
|
switch (state) {
|
|
|
|
is(s_idle) {
|
|
|
|
io.inner.acquire.ready := Bool(true)
|
|
|
|
when( io.inner.acquire.valid ) {
|
2014-12-12 10:11:08 +01:00
|
|
|
xact_uncached := c_acq.payload.uncached
|
|
|
|
xact_a_type := c_acq.payload.a_type
|
|
|
|
xact_addr := c_acq.payload.addr
|
|
|
|
xact_client_xact_id := c_acq.payload.client_xact_id
|
|
|
|
xact_data(UInt(0)) := c_acq.payload.data
|
|
|
|
xact_subblock := c_acq.payload.subblock
|
|
|
|
xact_src := c_acq.header.src
|
|
|
|
collect_cacq_data := co.messageHasData(c_acq.payload)
|
2014-10-08 07:33:10 +02:00
|
|
|
state := s_meta_read
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_meta_read) {
|
2014-11-20 00:55:25 +01:00
|
|
|
io.meta.read.valid := Bool(true)
|
|
|
|
when(io.meta.read.ready) { state := s_meta_resp }
|
2014-10-08 07:33:10 +02:00
|
|
|
}
|
|
|
|
is(s_meta_resp) {
|
2014-11-20 00:55:25 +01:00
|
|
|
when(io.meta.resp.valid) {
|
2014-12-12 10:11:08 +01:00
|
|
|
xact_tag_match := io.meta.resp.bits.tag_match
|
|
|
|
xact_meta := io.meta.resp.bits.meta
|
|
|
|
xact_way_en := io.meta.resp.bits.way_en
|
2014-11-20 00:55:25 +01:00
|
|
|
val coh = io.meta.resp.bits.meta.coh
|
|
|
|
val _tag_match = io.meta.resp.bits.tag_match
|
2014-10-24 06:50:03 +02:00
|
|
|
val _needs_writeback = !_tag_match && co.needsWriteback(coh)
|
2014-12-19 12:03:53 +01:00
|
|
|
val _needs_probes = _tag_match && co.requiresProbes(xact, coh)
|
2014-10-24 06:50:03 +02:00
|
|
|
val _is_hit = _tag_match && co.isHit(xact, coh)
|
2014-10-08 07:33:10 +02:00
|
|
|
when(_needs_probes) {
|
2014-12-19 12:03:53 +01:00
|
|
|
pending_probes := mask_incoherent(nCoherentClients-1,0)
|
|
|
|
release_count := co.dir.count(mask_incoherent)
|
2014-10-24 06:50:03 +02:00
|
|
|
crel_had_data := Bool(false)
|
2014-12-12 10:11:08 +01:00
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
state := Mux(_tag_match,
|
2014-12-19 12:03:53 +01:00
|
|
|
Mux(_needs_probes, s_probe, Mux(_is_hit, s_data_read, s_outer_read)), // Probe, hit or upgrade
|
|
|
|
Mux(_needs_writeback, s_wb_req, s_outer_read)) // Evict ifneedbe
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
2014-12-19 12:03:53 +01:00
|
|
|
is(s_wb_req) {
|
|
|
|
io.wb.req.valid := Bool(true)
|
|
|
|
when(io.wb.req.ready) { state := s_wb_resp }
|
|
|
|
}
|
|
|
|
is(s_wb_resp) {
|
|
|
|
when(io.wb.resp.valid) { state := s_outer_read }
|
|
|
|
}
|
2014-09-30 23:48:02 +02:00
|
|
|
is(s_probe) {
|
2014-12-19 12:03:53 +01:00
|
|
|
// Send probes
|
2014-12-16 04:23:13 +01:00
|
|
|
io.inner.probe.valid := !co.dir.none(pending_probes)
|
2014-10-24 06:50:03 +02:00
|
|
|
when(io.inner.probe.ready) {
|
2014-12-16 04:23:13 +01:00
|
|
|
pending_probes := co.dir.pop(pending_probes, curr_p_id)
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
// Handle releases, which may have data being written back
|
|
|
|
io.inner.release.ready := Bool(true)
|
2014-09-30 23:48:02 +02:00
|
|
|
when(io.inner.release.valid) {
|
2014-12-19 12:03:53 +01:00
|
|
|
xact_meta.coh := next_coh_on_rel
|
2014-12-12 10:11:08 +01:00
|
|
|
// Handle released dirty data
|
2014-09-30 23:48:02 +02:00
|
|
|
when(co.messageHasData(c_rel.payload)) {
|
2014-10-24 06:50:03 +02:00
|
|
|
crel_had_data := Bool(true)
|
2014-12-19 12:03:53 +01:00
|
|
|
//TODO make sure cacq data is actually present before merging
|
|
|
|
xact_data(crel_data_cnt) := mergeData(xact,
|
|
|
|
xact_data(crel_data_cnt),
|
|
|
|
c_rel.payload.data)
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-12-19 12:03:53 +01:00
|
|
|
// We don't decrement release_count until we've received all the data beats.
|
|
|
|
when(!co.messageHasData(c_rel.payload) || crel_data_done) {
|
|
|
|
release_count := release_count - UInt(1)
|
2014-10-24 06:50:03 +02:00
|
|
|
}
|
|
|
|
}
|
2014-12-19 12:03:53 +01:00
|
|
|
when(release_count === UInt(0)) {
|
|
|
|
state := Mux(is_hit, Mux(crel_had_data, s_data_write, s_data_read), s_outer_read)
|
2014-10-08 07:33:10 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_outer_read) {
|
2014-09-30 23:48:02 +02:00
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
io.outer.acquire.bits.payload := outer_read
|
|
|
|
when(io.outer.acquire.ready) {
|
2014-10-08 07:33:10 +02:00
|
|
|
state := s_outer_resp
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
is(s_outer_resp) {
|
|
|
|
io.outer.grant.ready := Bool(true)
|
|
|
|
when(io.outer.grant.valid) {
|
2014-12-12 10:11:08 +01:00
|
|
|
//TODO make sure cacq data is actually present before merging
|
|
|
|
xact_data(outer_data_resp_cnt) := mergeData(xact, xact_data(outer_data_resp_cnt),
|
|
|
|
io.outer.grant.bits.payload.data)
|
|
|
|
//TODO: set pending client state in xact_meta.coh
|
|
|
|
when(outer_data_resp_done) {
|
|
|
|
state := Mux(co.messageHasData(io.outer.grant.bits.payload),
|
2014-12-19 12:03:53 +01:00
|
|
|
s_data_write, s_data_read)
|
2014-12-12 10:11:08 +01:00
|
|
|
}
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
2014-12-19 12:03:53 +01:00
|
|
|
is(s_data_read) {
|
2014-11-20 00:55:25 +01:00
|
|
|
io.data.read.valid := Bool(true)
|
2014-12-12 10:11:08 +01:00
|
|
|
when(io.data.resp.valid) {
|
|
|
|
//TODO make sure cacq data is actually present before merging
|
|
|
|
xact_data(local_data_resp_cnt) := mergeData(xact, xact_data(local_data_resp_cnt),
|
|
|
|
io.data.resp.bits.data)
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-12-19 12:03:53 +01:00
|
|
|
when(local_data_read_done) { state := s_data_resp }
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2014-12-19 12:03:53 +01:00
|
|
|
is(s_data_resp) {
|
2014-11-20 00:55:25 +01:00
|
|
|
when(io.data.resp.valid) {
|
2014-12-12 10:11:08 +01:00
|
|
|
xact_data(local_data_resp_cnt) := mergeData(xact, xact_data(local_data_resp_cnt),
|
|
|
|
io.data.resp.bits.data)
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
2015-01-06 04:48:49 +01:00
|
|
|
when(local_data_resp_done) {
|
|
|
|
state := Mux(co.messageHasData(xact), s_data_write, s_meta_write)
|
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
}
|
|
|
|
is(s_data_write) {
|
2014-11-20 00:55:25 +01:00
|
|
|
io.data.write.valid := Bool(true)
|
2014-12-12 10:11:08 +01:00
|
|
|
when(local_data_write_done) {
|
2014-10-08 07:33:10 +02:00
|
|
|
state := s_meta_write
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|
2014-10-08 07:33:10 +02:00
|
|
|
is(s_meta_write) {
|
2014-11-20 00:55:25 +01:00
|
|
|
io.meta.write.valid := Bool(true)
|
|
|
|
when(io.meta.write.ready) { state := s_grant }
|
2014-10-08 07:33:10 +02:00
|
|
|
}
|
|
|
|
is(s_grant) {
|
|
|
|
io.inner.grant.valid := Bool(true)
|
2014-12-12 10:11:08 +01:00
|
|
|
when(!co.messageHasData(c_gnt.payload) || cgnt_data_done) {
|
2014-11-13 01:25:25 +01:00
|
|
|
state := Mux(co.requiresAckForGrant(c_gnt.payload),
|
2014-10-08 07:33:10 +02:00
|
|
|
s_busy, s_idle)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_busy) {
|
2014-10-24 06:50:03 +02:00
|
|
|
io.inner.finish.ready := Bool(true)
|
2014-10-08 07:33:10 +02:00
|
|
|
when(io.inner.finish.valid) { state := s_idle }
|
|
|
|
}
|
2014-09-30 23:48:02 +02:00
|
|
|
}
|
|
|
|
}
|