2014-04-23 01:55:35 +02:00
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package uncore
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import Chisel._
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2014-04-27 04:11:36 +02:00
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trait CacheConfig {
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2014-04-23 01:55:35 +02:00
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def sets: Int
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def ways: Int
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def tl: TileLinkConfiguration
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def as: AddressSpaceConfiguration
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def dm: Boolean
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def states: Int
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def lines: Int
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def tagbits: Int
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def idxbits: Int
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def offbits: Int
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def untagbits: Int
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def rowbits: Int
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}
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2014-04-27 04:11:36 +02:00
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case class L2CacheConfig(
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val sets: Int, val ways: Int,
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val nrpq: Int, val nsdq: Int,
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val nReleaseTransactions: Int,
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val nAcquireTransactions: Int,
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val tl: TileLinkConfiguration,
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val as: AddressSpaceConfiguration)
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extends CoherenceAgentConfiguration
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with CacheConfig
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{
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2014-04-23 01:55:35 +02:00
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def states = tl.co.nMasterStates
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def lines = sets*ways
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def dm = ways == 1
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def offbits = 0
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def lineaddrbits = tl.addrBits
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def idxbits = log2Up(sets)
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def waybits = log2Up(ways)
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def untagbits = offbits + idxbits
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def tagbits = lineaddrbits - idxbits
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2014-04-27 04:11:36 +02:00
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def wordbits = 64
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def wordbytes = wordbits/8
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def wordoffbits = log2Up(wordbytes)
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2014-04-23 01:55:35 +02:00
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def rowbits = tl.dataBits
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def rowbytes = rowbits/8
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def rowoffbits = log2Up(rowbytes)
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def refillcycles = tl.dataBits/(rowbits)
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def statebits = log2Up(states)
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require(states > 0)
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require(isPow2(sets))
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require(isPow2(ways)) // TODO: relax this
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2014-04-27 04:11:36 +02:00
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require(refillcycles == 1) //TODO: relax this?
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2014-04-23 01:55:35 +02:00
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}
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abstract trait CacheBundle extends Bundle {
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2014-04-27 04:11:36 +02:00
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implicit val cacheconf: CacheConfig
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override def clone = this.getClass.getConstructors.head.newInstance(cacheconf).asInstanceOf[this.type]
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2014-04-23 01:55:35 +02:00
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}
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abstract trait L2CacheBundle extends Bundle {
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2014-04-27 04:11:36 +02:00
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implicit val l2cacheconf: L2CacheConfig
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override def clone = this.getClass.getConstructors.head.newInstance(l2cacheconf).asInstanceOf[this.type]
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2014-04-23 01:55:35 +02:00
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}
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abstract class ReplacementPolicy {
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def way: UInt
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def miss: Unit
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def hit: Unit
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}
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2014-04-27 04:11:36 +02:00
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class RandomReplacement(implicit val cacheconf: CacheConfig) extends ReplacementPolicy {
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2014-04-23 01:55:35 +02:00
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private val replace = Bool()
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replace := Bool(false)
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val lfsr = LFSR16(replace)
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2014-04-27 04:11:36 +02:00
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def way = if(cacheconf.dm) UInt(0) else lfsr(log2Up(cacheconf.ways)-1,0)
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2014-04-23 01:55:35 +02:00
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def miss = replace := Bool(true)
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def hit = {}
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}
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2014-05-01 10:44:59 +02:00
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abstract class MetaData(implicit val cacheconf: CacheConfig) extends CacheBundle {
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2014-04-27 04:11:36 +02:00
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val tag = Bits(width = cacheconf.tagbits)
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2014-04-23 01:55:35 +02:00
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}
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2014-05-01 10:44:59 +02:00
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class L2MetaData(implicit val l2cacheconf: L2CacheConfig) extends MetaData
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with L2CacheBundle {
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val state = UInt(width = l2cacheconf.statebits)
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val sharers = Bits(width = l2cacheconf.tl.ln.nClients)
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}
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/*
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class L3MetaData(implicit conf: L3CacheConfig) extends MetaData()(conf) {
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val cstate = UInt(width = cacheconf.cstatebits)
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val mstate = UInt(width = cacheconf.mstatebits)
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val sharers = Bits(width = cacheconf.tl.ln.nClients)
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}
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*/
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2014-04-27 04:11:36 +02:00
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class MetaReadReq(implicit val cacheconf: CacheConfig) extends CacheBundle {
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val idx = Bits(width = cacheconf.idxbits)
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2014-04-23 01:55:35 +02:00
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}
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2014-05-01 10:44:59 +02:00
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class MetaWriteReq[T <: MetaData](gen: T)(implicit conf: CacheConfig) extends MetaReadReq {
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2014-04-23 01:55:35 +02:00
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val way_en = Bits(width = conf.ways)
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2014-05-01 10:44:59 +02:00
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val data = gen.clone
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override def clone = new MetaWriteReq(gen)(conf).asInstanceOf[this.type]
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2014-04-23 01:55:35 +02:00
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}
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2014-05-01 10:44:59 +02:00
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class MetaDataArray[T <: MetaData](resetMeta: T)(implicit conf: CacheConfig) extends Module {
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2014-04-23 01:55:35 +02:00
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implicit val tl = conf.tl
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2014-05-01 10:44:59 +02:00
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def gen = resetMeta.clone
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2014-04-23 01:55:35 +02:00
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val io = new Bundle {
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2014-04-24 01:24:20 +02:00
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val read = Decoupled(new MetaReadReq).flip
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2014-05-01 10:44:59 +02:00
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val write = Decoupled(new MetaWriteReq(gen)).flip
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val resp = Vec.fill(conf.ways){gen.asOutput}
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2014-04-23 01:55:35 +02:00
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}
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2014-05-01 10:44:59 +02:00
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val metabits = resetMeta.getWidth
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2014-04-23 01:55:35 +02:00
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val rst_cnt = Reg(init=UInt(0, log2Up(conf.sets+1)))
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val rst = rst_cnt < UInt(conf.sets)
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when (rst) { rst_cnt := rst_cnt+UInt(1) }
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2014-05-01 10:44:59 +02:00
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val tags = Mem(UInt(width = metabits*conf.ways), conf.sets, seqRead = true)
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2014-04-23 01:55:35 +02:00
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when (rst || io.write.valid) {
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val addr = Mux(rst, rst_cnt, io.write.bits.idx)
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2014-05-01 10:44:59 +02:00
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val data = Mux(rst, resetMeta, io.write.bits.data).toBits
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2014-04-23 01:55:35 +02:00
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val mask = Mux(rst, SInt(-1), io.write.bits.way_en)
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2014-05-01 10:44:59 +02:00
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tags.write(addr, Fill(conf.ways, data), FillInterleaved(metabits, mask))
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2014-04-23 01:55:35 +02:00
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}
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val tag = tags(RegEnable(io.read.bits.idx, io.read.valid))
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for (w <- 0 until conf.ways) {
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2014-05-01 10:44:59 +02:00
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val m = tag(metabits*(w+1)-1, metabits*w)
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io.resp(w) := gen.fromBits(m)
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2014-04-23 01:55:35 +02:00
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}
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io.read.ready := !rst && !io.write.valid // so really this could be a 6T RAM
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io.write.ready := !rst
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}
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2014-04-27 04:11:36 +02:00
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class L2DataReadReq(implicit val l2cacheconf: L2CacheConfig) extends L2CacheBundle {
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val way_en = Bits(width = l2cacheconf.ways)
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val addr = Bits(width = l2cacheconf.tl.addrBits)
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2014-04-23 01:55:35 +02:00
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}
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class L2DataWriteReq(implicit conf: L2CacheConfig) extends L2DataReadReq()(conf) {
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val wmask = Bits(width = conf.tl.writeMaskBits)
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2014-04-27 04:11:36 +02:00
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val data = Bits(width = conf.tl.dataBits)
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2014-04-23 01:55:35 +02:00
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}
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class L2DataArray(implicit conf: L2CacheConfig) extends Module {
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val io = new Bundle {
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val read = Decoupled(new L2DataReadReq).flip
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val write = Decoupled(new L2DataWriteReq).flip
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2014-04-27 04:11:36 +02:00
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val resp = Vec.fill(conf.ways){Bits(OUTPUT, conf.tl.dataBits)}
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2014-04-23 01:55:35 +02:00
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}
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2014-04-27 04:11:36 +02:00
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val waddr = io.write.bits.addr
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val raddr = io.read.bits.addr
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val wmask = FillInterleaved(conf.wordbits, io.write.bits.wmask)
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2014-04-23 01:55:35 +02:00
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for (w <- 0 until conf.ways) {
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val array = Mem(Bits(width=conf.rowbits), conf.sets*conf.refillcycles, seqRead = true)
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when (io.write.bits.way_en(w) && io.write.valid) {
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array.write(waddr, io.write.bits.data, wmask)
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}
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io.resp(w) := array(RegEnable(raddr, io.read.bits.way_en(w) && io.read.valid))
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}
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io.read.ready := Bool(true)
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io.write.ready := Bool(true)
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}
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2014-05-01 10:44:59 +02:00
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trait L2InternalRequestState extends L2CacheBundle {
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2014-04-27 04:11:36 +02:00
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val tag_match = Bool()
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2014-05-01 10:44:59 +02:00
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val old_meta = new L2MetaData
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val way_en = Bits(width = l2cacheconf.ways)
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2014-04-27 04:11:36 +02:00
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}
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2014-05-01 10:44:59 +02:00
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class L2InternalAcquire(implicit val l2cacheconf: L2CacheConfig) extends Acquire()(l2cacheconf.tl)
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with L2InternalRequestState
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2014-04-27 04:11:36 +02:00
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2014-05-01 10:44:59 +02:00
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class L2InternalRelease(implicit val l2cacheconf: L2CacheConfig) extends Release()(l2cacheconf.tl)
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with L2InternalRequestState
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2014-04-27 04:11:36 +02:00
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class InternalTileLinkIO(implicit val l2cacheconf: L2CacheConfig) extends L2CacheBundle {
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implicit val (tl, ln) = (l2cacheconf.tl, l2cacheconf.tl.ln)
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2014-05-01 10:44:59 +02:00
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val acquire = new DecoupledIO(new LogicalNetworkIO(new L2InternalAcquire))
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2014-04-27 04:11:36 +02:00
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val probe = new DecoupledIO(new LogicalNetworkIO(new Probe)).flip
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2014-05-01 10:44:59 +02:00
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val release = new DecoupledIO(new LogicalNetworkIO(new L2InternalRelease))
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2014-04-27 04:11:36 +02:00
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val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip
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val finish = new DecoupledIO(new LogicalNetworkIO(new Finish))
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}
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class L2HellaCache(bankId: Int)(implicit conf: L2CacheConfig) extends CoherenceAgent {
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2014-04-23 01:55:35 +02:00
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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2014-04-27 04:11:36 +02:00
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val tshrfile = Module(new TSHRFile(bankId))
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2014-05-01 10:44:59 +02:00
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// tags
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val meta = Module(new MetaDataArray(new L2MetaData))
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// data
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val data = Module(new L2DataArray)
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// replacement policy
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val replacer = new RandomReplacement
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/*
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val s1_replaced_way_en = UIntToOH(replacer.way)
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val s2_replaced_way_en = UIntToOH(RegEnable(replacer.way, s1_clk_en))
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val s2_repl_meta = Mux1H(s2_replaced_way_en, wayMap((w: Int) =>
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RegEnable(meta.io.resp(w), s1_clk_en && s1_replaced_way_en(w))).toSeq)
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*/
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2014-04-30 01:49:18 +02:00
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tshrfile.io.inner <> io.inner
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io.outer <> tshrfile.io.outer
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2014-04-27 04:11:36 +02:00
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io.incoherent <> tshrfile.io.incoherent
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}
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class TSHRFile(bankId: Int)(implicit conf: L2CacheConfig) extends Module {
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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val io = new Bundle {
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2014-04-30 01:49:18 +02:00
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val inner = (new InternalTileLinkIO).flip
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2014-04-27 04:11:36 +02:00
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val outer = new UncachedTileLinkIO
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val incoherent = Vec.fill(ln.nClients){Bool()}.asInput
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val meta_read_req = Decoupled(new MetaReadReq)
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2014-05-01 10:44:59 +02:00
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val meta_write_req = Decoupled(new MetaWriteReq(new L2MetaData))
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val data_read_req = Decoupled(new L2DataReadReq)
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val data_write_req = Decoupled(new L2DataWriteReq)
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2014-04-27 04:11:36 +02:00
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}
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// Create TSHRs for outstanding transactions
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2014-04-23 01:55:35 +02:00
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val nTrackers = conf.nReleaseTransactions + conf.nAcquireTransactions
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val trackerList = (0 until conf.nReleaseTransactions).map(id => Module(new L2VoluntaryReleaseTracker(id, bankId))) ++
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(conf.nReleaseTransactions until nTrackers).map(id => Module(new L2AcquireTracker(id, bankId)))
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// Propagate incoherence flags
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trackerList.map(_.io.tile_incoherent := io.incoherent.toBits)
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// Handle acquire transaction initiation
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2014-04-30 01:49:18 +02:00
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val acquire = io.inner.acquire
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2014-04-23 01:55:35 +02:00
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val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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val block_acquires = any_acquire_conflict
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val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
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for( i <- 0 until trackerList.size ) {
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2014-04-30 01:49:18 +02:00
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val t = trackerList(i).io.inner
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2014-04-23 01:55:35 +02:00
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alloc_arb.io.in(i).valid := t.acquire.ready
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t.acquire.bits := acquire.bits
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t.acquire.valid := alloc_arb.io.in(i).ready
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}
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2014-04-30 01:49:18 +02:00
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acquire.ready := trackerList.map(_.io.inner.acquire.ready).reduce(_||_) && !block_acquires
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2014-04-23 01:55:35 +02:00
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alloc_arb.io.out.ready := acquire.valid && !block_acquires
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// Handle probe request generation
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val probe_arb = Module(new Arbiter(new LogicalNetworkIO(new Probe), trackerList.size))
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2014-04-30 01:49:18 +02:00
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io.inner.probe <> probe_arb.io.out
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probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.probe }
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2014-04-23 01:55:35 +02:00
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// Handle releases, which might be voluntary and might have data
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2014-04-30 01:49:18 +02:00
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val release = io.inner.release
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2014-04-23 01:55:35 +02:00
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val voluntary = co.isVoluntary(release.bits.payload)
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val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
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val block_releases = Bool(false)
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val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
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//val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UInt(0)), release.bits.payload.master_xact_id) // TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
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val release_idx = Mux(voluntary, UInt(0), release.bits.payload.master_xact_id)
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for( i <- 0 until trackerList.size ) {
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2014-04-30 01:49:18 +02:00
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val t = trackerList(i).io.inner
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2014-04-23 01:55:35 +02:00
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t.release.bits := release.bits
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t.release.valid := release.valid && (release_idx === UInt(i)) && !block_releases
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}
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2014-04-30 01:49:18 +02:00
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release.ready := Vec(trackerList.map(_.io.inner.release.ready)).read(release_idx) && !block_releases
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2014-04-23 01:55:35 +02:00
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// Reply to initial requestor
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val grant_arb = Module(new Arbiter(new LogicalNetworkIO(new Grant), trackerList.size))
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.grant <> grant_arb.io.out
|
|
|
|
grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.inner.grant }
|
2014-04-23 01:55:35 +02:00
|
|
|
|
|
|
|
// Free finished transactions
|
2014-04-30 01:49:18 +02:00
|
|
|
val ack = io.inner.finish
|
|
|
|
trackerList.map(_.io.inner.finish.valid := ack.valid)
|
|
|
|
trackerList.map(_.io.inner.finish.bits := ack.bits)
|
2014-04-23 01:55:35 +02:00
|
|
|
ack.ready := Bool(true)
|
|
|
|
|
|
|
|
// Create an arbiter for the one memory port
|
|
|
|
val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size))
|
2014-04-30 01:49:18 +02:00
|
|
|
outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.outer }
|
2014-04-27 04:11:36 +02:00
|
|
|
io.outer <> outer_arb.io.out
|
2014-04-23 01:55:35 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
abstract class L2XactTracker()(implicit conf: L2CacheConfig) extends Module {
|
|
|
|
implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
|
|
|
|
val io = new Bundle {
|
2014-04-30 01:49:18 +02:00
|
|
|
val inner = (new InternalTileLinkIO).flip
|
|
|
|
val outer = new UncachedTileLinkIO
|
2014-04-23 01:55:35 +02:00
|
|
|
val tile_incoherent = Bits(INPUT, ln.nClients)
|
|
|
|
val has_acquire_conflict = Bool(OUTPUT)
|
|
|
|
val has_release_conflict = Bool(OUTPUT)
|
|
|
|
}
|
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
val c_acq = io.inner.acquire.bits
|
|
|
|
val c_rel = io.inner.release.bits
|
|
|
|
val c_gnt = io.inner.grant.bits
|
|
|
|
val c_ack = io.inner.finish.bits
|
|
|
|
val m_gnt = io.outer.grant.bits
|
2014-04-23 01:55:35 +02:00
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
class L2VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: L2CacheConfig) extends L2XactTracker()(conf) {
|
|
|
|
val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(UInt(), 4)
|
|
|
|
val state = Reg(init=s_idle)
|
|
|
|
val xact = Reg{ new Release }
|
|
|
|
val init_client_id = Reg(init=UInt(0, width = log2Up(ln.nClients)))
|
2014-04-30 01:49:18 +02:00
|
|
|
val incoming_rel = io.inner.release.bits
|
2014-04-23 01:55:35 +02:00
|
|
|
|
|
|
|
io.has_acquire_conflict := Bool(false)
|
|
|
|
io.has_release_conflict := co.isCoherenceConflict(xact.addr, incoming_rel.payload.addr) &&
|
|
|
|
(state != s_idle)
|
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.grant.ready := Bool(false)
|
|
|
|
io.outer.acquire.valid := Bool(false)
|
|
|
|
io.outer.acquire.bits.header.src := UInt(bankId)
|
|
|
|
//io.outer.acquire.bits.header.dst TODO
|
|
|
|
io.outer.acquire.bits.payload := Acquire(co.getUncachedWriteAcquireType,
|
2014-04-23 01:55:35 +02:00
|
|
|
xact.addr,
|
|
|
|
UInt(trackerId),
|
|
|
|
xact.data)
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.acquire.ready := Bool(false)
|
|
|
|
io.inner.probe.valid := Bool(false)
|
|
|
|
io.inner.release.ready := Bool(false)
|
|
|
|
io.inner.grant.valid := Bool(false)
|
|
|
|
io.inner.grant.bits.header.src := UInt(bankId)
|
|
|
|
io.inner.grant.bits.header.dst := init_client_id
|
|
|
|
io.inner.grant.bits.payload := Grant(co.getGrantType(xact, UInt(0)),
|
2014-04-23 01:55:35 +02:00
|
|
|
xact.client_xact_id,
|
|
|
|
UInt(trackerId))
|
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
is(s_idle) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.release.ready := Bool(true)
|
|
|
|
when( io.inner.release.valid ) {
|
2014-04-23 01:55:35 +02:00
|
|
|
xact := incoming_rel.payload
|
|
|
|
init_client_id := incoming_rel.header.src
|
|
|
|
state := Mux(co.messageHasData(incoming_rel.payload), s_mem, s_ack)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_mem) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
when(io.outer.acquire.ready) { state := s_ack }
|
2014-04-23 01:55:35 +02:00
|
|
|
}
|
|
|
|
is(s_ack) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.grant.valid := Bool(true)
|
|
|
|
when(io.inner.grant.ready) { state := s_idle }
|
2014-04-23 01:55:35 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
class L2AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: L2CacheConfig) extends L2XactTracker()(conf) {
|
|
|
|
val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_busy :: Nil = Enum(UInt(), 6)
|
|
|
|
val state = Reg(init=s_idle)
|
|
|
|
val xact = Reg{ new Acquire }
|
|
|
|
val init_client_id = Reg(init=UInt(0, width = log2Up(ln.nClients)))
|
|
|
|
//TODO: Will need id reg for merged release xacts
|
|
|
|
|
|
|
|
val init_sharer_cnt = Reg(init=UInt(0, width = log2Up(ln.nClients)))
|
|
|
|
val release_count = if (ln.nClients == 1) UInt(0) else Reg(init=UInt(0, width = log2Up(ln.nClients)))
|
|
|
|
val probe_flags = Reg(init=Bits(0, width = ln.nClients))
|
|
|
|
val curr_p_id = PriorityEncoder(probe_flags)
|
|
|
|
|
|
|
|
val pending_outer_write = co.messageHasData(xact)
|
|
|
|
val pending_outer_read = co.needsOuterRead(xact.a_type, UInt(0))
|
|
|
|
val outer_write_acq = Acquire(co.getUncachedWriteAcquireType,
|
|
|
|
xact.addr, UInt(trackerId), xact.data)
|
|
|
|
val outer_write_rel = Acquire(co.getUncachedWriteAcquireType,
|
|
|
|
xact.addr, UInt(trackerId), c_rel.payload.data)
|
|
|
|
val outer_read = Acquire(co.getUncachedReadAcquireType, xact.addr, UInt(trackerId))
|
|
|
|
|
|
|
|
val probe_initial_flags = Bits(width = ln.nClients)
|
|
|
|
probe_initial_flags := Bits(0)
|
|
|
|
if (ln.nClients > 1) {
|
|
|
|
// issue self-probes for uncached read xacts to facilitate I$ coherence
|
2014-04-30 01:49:18 +02:00
|
|
|
val probe_self = Bool(true) //co.needsSelfProbe(io.inner.acquire.bits.payload)
|
2014-04-23 01:55:35 +02:00
|
|
|
val myflag = Mux(probe_self, Bits(0), UIntToOH(c_acq.header.src(log2Up(ln.nClients)-1,0)))
|
|
|
|
probe_initial_flags := ~(io.tile_incoherent | myflag)
|
|
|
|
}
|
|
|
|
|
|
|
|
io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, c_acq.payload.addr) && (state != s_idle)
|
|
|
|
io.has_release_conflict := co.isCoherenceConflict(xact.addr, c_rel.payload.addr) && (state != s_idle)
|
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(false)
|
|
|
|
io.outer.acquire.bits.header.src := UInt(bankId)
|
|
|
|
//io.outer.acquire.bits.header.dst TODO
|
|
|
|
io.outer.acquire.bits.payload := outer_read
|
|
|
|
io.outer.grant.ready := io.inner.grant.ready
|
2014-04-23 01:55:35 +02:00
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.probe.valid := Bool(false)
|
|
|
|
io.inner.probe.bits.header.src := UInt(bankId)
|
|
|
|
io.inner.probe.bits.header.dst := curr_p_id
|
|
|
|
io.inner.probe.bits.payload := Probe(co.getProbeType(xact.a_type, UInt(0)),
|
2014-04-23 01:55:35 +02:00
|
|
|
xact.addr,
|
|
|
|
UInt(trackerId))
|
|
|
|
|
|
|
|
val grant_type = co.getGrantType(xact.a_type, init_sharer_cnt)
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.grant.valid := Bool(false)
|
|
|
|
io.inner.grant.bits.header.src := UInt(bankId)
|
|
|
|
io.inner.grant.bits.header.dst := init_client_id
|
|
|
|
io.inner.grant.bits.payload := Grant(grant_type,
|
2014-04-23 01:55:35 +02:00
|
|
|
xact.client_xact_id,
|
|
|
|
UInt(trackerId),
|
|
|
|
m_gnt.payload.data)
|
|
|
|
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.acquire.ready := Bool(false)
|
|
|
|
io.inner.release.ready := Bool(false)
|
2014-04-23 01:55:35 +02:00
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
is(s_idle) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.acquire.ready := Bool(true)
|
2014-04-23 01:55:35 +02:00
|
|
|
val needs_outer_write = co.messageHasData(c_acq.payload)
|
|
|
|
val needs_outer_read = co.needsOuterRead(c_acq.payload.a_type, UInt(0))
|
2014-04-30 01:49:18 +02:00
|
|
|
when( io.inner.acquire.valid ) {
|
2014-04-23 01:55:35 +02:00
|
|
|
xact := c_acq.payload
|
|
|
|
init_client_id := c_acq.header.src
|
|
|
|
init_sharer_cnt := UInt(ln.nClients) // TODO: Broadcast only
|
|
|
|
probe_flags := probe_initial_flags
|
|
|
|
if(ln.nClients > 1) {
|
|
|
|
release_count := PopCount(probe_initial_flags)
|
|
|
|
state := Mux(probe_initial_flags.orR, s_probe,
|
|
|
|
Mux(needs_outer_write, s_mem_write,
|
|
|
|
Mux(needs_outer_read, s_mem_read, s_make_grant)))
|
|
|
|
} else state := Mux(needs_outer_write, s_mem_write,
|
|
|
|
Mux(needs_outer_read, s_mem_read, s_make_grant))
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_probe) {
|
|
|
|
// Generate probes
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.probe.valid := probe_flags.orR
|
|
|
|
when(io.inner.probe.ready) {
|
2014-04-23 01:55:35 +02:00
|
|
|
probe_flags := probe_flags & ~(UIntToOH(curr_p_id))
|
|
|
|
}
|
|
|
|
|
|
|
|
// Handle releases, which may have data to be written back
|
2014-04-30 01:49:18 +02:00
|
|
|
when(io.inner.release.valid) {
|
2014-04-23 01:55:35 +02:00
|
|
|
when(co.messageHasData(c_rel.payload)) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
io.outer.acquire.bits.payload := outer_write_rel
|
|
|
|
when(io.outer.acquire.ready) {
|
|
|
|
io.inner.release.ready := Bool(true)
|
2014-04-23 01:55:35 +02:00
|
|
|
if(ln.nClients > 1) release_count := release_count - UInt(1)
|
|
|
|
when(release_count === UInt(1)) {
|
|
|
|
state := Mux(pending_outer_write, s_mem_write,
|
|
|
|
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} .otherwise {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.release.ready := Bool(true)
|
2014-04-23 01:55:35 +02:00
|
|
|
if(ln.nClients > 1) release_count := release_count - UInt(1)
|
|
|
|
when(release_count === UInt(1)) {
|
|
|
|
state := Mux(pending_outer_write, s_mem_write,
|
|
|
|
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_mem_read) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
io.outer.acquire.bits.payload := outer_read
|
|
|
|
when(io.outer.acquire.ready) {
|
2014-04-23 01:55:35 +02:00
|
|
|
state := Mux(co.requiresAckForGrant(grant_type), s_busy, s_idle)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_mem_write) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.outer.acquire.valid := Bool(true)
|
|
|
|
io.outer.acquire.bits.payload := outer_write_acq
|
|
|
|
when(io.outer.acquire.ready) {
|
2014-04-23 01:55:35 +02:00
|
|
|
state := Mux(pending_outer_read, s_mem_read, s_make_grant)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_make_grant) {
|
2014-04-30 01:49:18 +02:00
|
|
|
io.inner.grant.valid := Bool(true)
|
|
|
|
when(io.inner.grant.ready) {
|
2014-04-23 01:55:35 +02:00
|
|
|
state := Mux(co.requiresAckForGrant(grant_type), s_busy, s_idle)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_busy) { // Nothing left to do but wait for transaction to complete
|
2014-04-30 01:49:18 +02:00
|
|
|
when(io.outer.grant.valid && m_gnt.payload.client_xact_id === UInt(trackerId)) {
|
|
|
|
io.inner.grant.valid := Bool(true)
|
2014-04-23 01:55:35 +02:00
|
|
|
}
|
2014-04-30 01:49:18 +02:00
|
|
|
when(io.inner.finish.valid && c_ack.payload.master_xact_id === UInt(trackerId)) {
|
2014-04-23 01:55:35 +02:00
|
|
|
state := s_idle
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|