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63 Commits

Author SHA1 Message Date
Klemens Schölhorn 552553e526 Load 32 MiB bootimage from a 2048 sector offset (first partiton) 2018-06-13 00:34:19 +02:00
Klemens Schölhorn ee888b8c7b Rebuild when changing the bootloader 2018-06-13 00:33:46 +02:00
Klemens Schölhorn c812a8878f Properly set clock frequencies 2018-06-06 01:05:36 +02:00
Klemens Schölhorn 2c74ef7f03 Use correct frequency for the sd-spi interface 2018-05-19 19:04:56 +02:00
Klemens Schölhorn c27ee2215c Print everything send over serial to the terminal 2018-05-19 19:04:11 +02:00
Klemens Schölhorn ec4e3ec36d Use rocket config with fpu and mmu for booting linux 2018-05-19 19:00:57 +02:00
Klemens Schölhorn 87bb3a5f24 Use correct clock period and memory size in config 2018-05-14 20:10:08 +02:00
Klemens Schölhorn a3f166d5a2 Pull in memory and terminal improvements 2018-05-14 20:09:55 +02:00
Klemens Schölhorn 175ed051d3 Pull in the new XilinxML507MIGToTL implementation 2018-05-10 21:43:51 +02:00
Klemens Schölhorn 291a765b8d Switch to new XilinxML507MIG and connect top level signals 2018-05-10 00:37:00 +02:00
Klemens Schölhorn 7b46ed6b7c Move ml507 mig TL stub into fpga-shells 2018-05-09 23:22:53 +02:00
Klemens Schölhorn 0cb89fd675 Add fragmenter in front of TLMemoryML507 and implementation notes 2018-05-03 01:57:06 +02:00
Klemens Schölhorn 7a514c6477 Point all submodules to tiband 2018-05-01 00:14:53 +02:00
Klemens Schölhorn e57dfd0f63 Update rocket-chip to fix rom generation 2018-05-01 00:11:11 +02:00
Klemens Schölhorn df44d1a3bc Make DIP switches available as GPIO register 2018-05-01 00:09:14 +02:00
Klemens Schölhorn 4f950772a1 Use 80 MHz for rocket and 48 MHz for the terminal 2018-04-30 22:54:57 +02:00
Klemens Schölhorn 97eeb7af29 Add terminal peripheral (in same clock domain for now) 2018-04-30 00:54:21 +02:00
Klemens Schölhorn 1cb558d2ea ml507: Don't accept any messages in the stub memory slave 2018-04-24 00:50:13 +02:00
Klemens Schölhorn d749f87696 ml507: Remove redundant clock definition 2018-04-24 00:49:39 +02:00
Klemens Schölhorn c10d2378e7 Disable TLMonitors 2018-04-19 01:34:10 +02:00
Klemens Schölhorn 2b5509009c Increase gpio width to 8 2018-04-19 01:33:24 +02:00
Klemens Schölhorn 06a623a05a Update to latest ml507 shell 2018-04-19 01:33:09 +02:00
Klemens Schölhorn 48f3a7e590 Reduce rocket to a single core 
More than one core does not fit on the ml507 and is more than enough for
booting linux and executing basic utilities.
 2018-04-18 00:28:01 +02:00
Klemens Schölhorn 7449f52b9a Update to latest ml507 shell 2018-04-18 00:27:45 +02:00
Klemens Schölhorn 212821fe4d Switch to the new ML507Shell 
This enables synthesis for the first time!
 2018-04-12 00:50:38 +02:00
Klemens Schölhorn 8e4eaf6603 Add TLMemoryML507 stub and integration 2018-04-11 22:26:14 +02:00
Klemens Schölhorn 0134a8f4dc Remove vc707 memory interface from ml507 2018-04-11 20:55:00 +02:00
Klemens Schölhorn 5fdadd244c Add makefile and config for the ml507 board 
The config is based on the u500vc707devkit config.
 2018-04-11 20:09:05 +02:00
Henry Styles cd9a525a66
Merge pull request #50 from sifive/update_readme_vc707_vivado2016dot4 
U500 VC707 FPGA Dev Kit : update required Vivado version from 2016.1 to 2016.4
 2018-04-06 10:55:00 -07:00
Henry Styles 0e77cb9d87 U500 VC707 FPGA Dev Kit : update required Vivado version from 2016.1 to 2016.4 to fix synthesis bug effecting debug module 2018-04-06 10:54:03 -07:00
Henry Styles c0a2869e56
Merge pull request #49 from sifive/update_vc707_sdboot 
Correct GPIO/SPI/UART base address for VC707 SDBOOT
 2018-04-05 22:13:22 -07:00
Henry Styles 0663bb7627 Correct GPIO/SPI/UART base addresse for vc707 sdboot 2018-04-05 22:11:39 -07:00
Wesley W. Terpstra fff18810cd
Merge pull request #48 from sifive/chiplink 
Add a VC707 chiplink slave target
 2018-03-22 20:38:30 -07:00
Wesley W. Terpstra 41f29484fd iofpga: add a vc707 chiplink slave target 2018-03-22 20:37:50 -07:00
Wesley W. Terpstra ac070218d1 submodule: bump to master 2018-03-22 18:18:28 -07:00
Wesley W. Terpstra d3fa3c8652 build.sbt: update to rocket's scala version 2018-03-22 18:10:19 -07:00
Wesley W. Terpstra 9b3763ea92
Merge pull request #47 from sifive/bump-repos 
build: update all submodules to their current master
 2018-03-10 00:55:11 -08:00
Wesley W. Terpstra 1445a381a1 platforms: fixup to new package names 2018-03-05 15:45:01 -08:00
Wesley W. Terpstra 6c9b159659 submodules: bump again for the latest refactor 2018-03-05 15:14:23 -08:00
Wesley W. Terpstra c076d53fe9 fpga-shells: bump to fix timing closure 2018-02-25 15:21:36 -08:00
Wesley W. Terpstra 756e2e82a1 build: update all submodules to their current master 2018-02-25 10:33:25 -08:00
Megan Wachs 3cdb87e613
Merge pull request #44 from sifive/bump-sifive-blocks 
bump sifive-blocks for GPIO IOF fix
 2017-11-22 13:42:22 -08:00
Megan Wachs 03cbe72c3e bump sifive-blocks for GPIO IOF fix 2017-11-22 12:26:53 -08:00
Megan Wachs 5a1d816f48 Add links to some documents for E300 Arty Dev Kit (#41) 2017-11-03 16:59:30 -07:00
Wesley W. Terpstra 07c6e4abd4
Merge pull request #40 from sifive/bump 
Bump all hardware to the newest versions
 2017-11-03 16:59:17 -07:00
Wesley W. Terpstra e1673b8670 README: note the vivado version requirements 2017-11-03 16:10:41 -07:00
Wesley W. Terpstra 4297b22472 unleashed: build quad-core instead 
Because there are boot loaders out there that disable core 0, let's
make sure the open source design has >1 core to prevent these images
from hanging. We should also change freedom-u-sdk to check using DTS
to determine which cores to disable to properly fix this problem.
 2017-11-03 16:10:41 -07:00
Wesley W. Terpstra 9f0877fc85 sdboot: support SMP boot 2017-11-03 16:10:41 -07:00
Wesley W. Terpstra c965442560 u500: enable FPU; needed by linux 2017-11-03 16:10:41 -07:00
Wesley W. Terpstra 9cb03a3708 README: update location of built files 2017-11-03 16:10:41 -07:00