iofpga: add a vc707 chiplink slave target
This commit is contained in:
Wesley W. Terpstra
parent
ac070218d1
commit
41f29484fd
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# See LICENSE for license details.
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base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
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BUILD_DIR := $(base_dir)/builds/u500vc707iofpga
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FPGA_DIR := $(base_dir)/fpga-shells/xilinx
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MODEL := IOFPGAChip
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PROJECT := sifive.freedom.unleashed.vc707.iofpga
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export CONFIG_PROJECT := sifive.freedom.unleashed.vc707.iofpga
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export CONFIG := IOFPGAConfig
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export BOARD := vc707
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rocketchip_dir := $(base_dir)/rocket-chip
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sifiveblocks_dir := $(base_dir)/sifive-blocks
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VSRCS := \
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$(rocketchip_dir)/vsrc/AsyncResetReg.v \
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$(rocketchip_dir)/vsrc/plusarg_reader.v \
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$(sifiveblocks_dir)/vsrc/SRLatch.v \
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$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
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$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
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$(FPGA_DIR)/$(BOARD)/vsrc/vc707reset.v \
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$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
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include common.mk
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// See LICENSE for license details.
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package sifive.freedom.unleashed.vc707.iofpga
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import Chisel._
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import chisel3.experimental.{withClockAndReset}
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.util.{ElaborationArtefacts,ResetCatchAndSync}
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.pinctrl.{BasePin}
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import sifive.blocks.devices.msi._
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import sifive.blocks.devices.chiplink._
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import sifive.fpgashells.shell.xilinx.vc707shell.{VC707Shell,HasPCIe,HasDDR3,HasVC707ChipLink}
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import sifive.fpgashells.ip.xilinx.{IOBUF,vc707_sys_clock_mmcm3}
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import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
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import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
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import sifive.freedom.unleashed.u500vc707devkit.FreedomUVC707Config
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//-------------------------------------------------------------------------
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// PinGen
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//-------------------------------------------------------------------------
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object PinGen {
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def apply(): BasePin = {
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new BasePin()
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}
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}
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//-------------------------------------------------------------------------
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// ShadowRAMHack -- shadow 512MiB of DDR at 0x6000_0000 from 0x30_0000_000
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// this makes it possible to boot linux using FPGA DDR
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//-------------------------------------------------------------------------
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class ShadowRAMHack(implicit p: Parameters) extends LazyModule
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{
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val from = AddressSet(0x60000000L, 0x1fffffffL)
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val to = AddressSet(0x3000000000L, 0x1fffffffL)
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val node = TLAdapterNode(
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clientFn = {cp => cp },
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managerFn = { mp =>
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require (mp.managers.size == 1)
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mp.copy(managers = mp.managers.map { m =>
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m.copy(address = m.address ++ Seq(from))
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})
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})
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, _), (out, _)) =>
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out <> in
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out.a.bits.address := Mux(
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from.contains(in.a.bits.address),
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in.a.bits.address + UInt(to.base - from.base),
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in.a.bits.address)
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}
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}
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}
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//-------------------------------------------------------------------------
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// IOFPGAChip
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//-------------------------------------------------------------------------
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class IOFPGA(
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localRoute: Seq[AddressSet],
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ddrparams: XilinxVC707MIGParams,
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chiplinkparams: ChipLinkParams,
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gpioparams: GPIOParams)(implicit p: Parameters) extends LazyModule
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{
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val link = LazyModule(new ChipLink(chiplinkparams))
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val sbar = LazyModule(new TLXbar)
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val xbar = LazyModule(new TLXbar)
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val mbar = LazyModule(new TLXbar)
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val serr = LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x2800000000L, 0xffffffffL)), 8, 128, true), beatBytes = 8))
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val gpio = LazyModule(new TLGPIO(w = 8, c = gpioparams))
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val xilinxvc707mig = LazyModule(new XilinxVC707MIG(ddrparams))
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val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
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val hack = LazyModule(new ShadowRAMHack)
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val msimaster = LazyModule(new MSIMaster(Seq(MSITarget(address=0x2020000, spacing=4, number=10))))
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private def filter(m: TLManagerParameters) = // keep only managers that are locally routed
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if (m.address.exists(a => localRoute.exists(_.overlaps(a)))) Some(m) else None
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// local master Xbar
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mbar.node := msimaster.masterNode
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mbar.node := TLFIFOFixer() := xilinxvc707pcie.crossTLOut := xilinxvc707pcie.master
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// split local master traffic either to local routing or off-chip
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link.node := TLBuffer() := mbar.node
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xbar.node := TLFilter(filter) := TLBuffer() := mbar.node
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xbar.node := TLBuffer() := link.node
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// receive traffic either from local routing or from off-chip
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sbar.node := TLBuffer() := TLAtomicAutomata() := TLFIFOFixer() := TLHintHandler() := TLBuffer() := TLWidthWidget(4) := xbar.node
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// local slave Xbar
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serr.node := sbar.node
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gpio.node := TLFragmenter(8,64,true) := sbar.node
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xilinxvc707mig.node := hack.node := sbar.node
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xilinxvc707pcie.slave := xilinxvc707pcie.crossTLIn := TLWidthWidget(8) := sbar.node
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xilinxvc707pcie.control := xilinxvc707pcie.crossTLIn := TLWidthWidget(8) := sbar.node
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// interrupts are fed into chiplink via MSI
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msimaster.intNode := xilinxvc707pcie.crossIntOut := xilinxvc707pcie.intnode
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msimaster.intNode := gpio.intnode
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lazy val module = new LazyModuleImp(this) {
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val io = IO (new Bundle {
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val chiplink = new WideDataLayerPort(chiplinkparams)
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val gpio = new GPIOPortIO(gpioparams)
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val xilinxvc707mig = new XilinxVC707MIGIO(AddressRange.fromSets(ddrparams.address).head.size)
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val xilinxvc707pcie = new XilinxVC707PCIeX1IO
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val rxlocked = Bool(INPUT)
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})
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io.xilinxvc707pcie <> xilinxvc707pcie.module.io.port
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xilinxvc707pcie.module.clock := xilinxvc707pcie.module.io.port.axi_aclk_out
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xilinxvc707pcie.module.reset := ~io.xilinxvc707pcie.axi_aresetn
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io.xilinxvc707mig <> xilinxvc707mig.module.io.port
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// Hold ChipLink in reset for a bit after power-on
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val timer = RegInit(UInt(255, width=8))
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timer := timer - timer.orR
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io.chiplink <> link.module.io.port
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link.module.io.c2b_clk := clock
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link.module.io.c2b_rst := ResetCatchAndSync(clock, reset || timer.orR || !io.rxlocked)
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io.gpio <> gpio.module.io.port
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}
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}
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class IOFPGAChip(implicit override val p: Parameters) extends VC707Shell
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with HasVC707ChipLink {
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val ddrParams = XilinxVC707MIGParams(address = Seq(AddressSet(0x3000000000L, 0xFFFFFFFFL))) // 192GB - 196GB (behind L2)
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val chipLinkParams = ChipLinkParams(
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TLUH = AddressSet.misaligned(0, 0x40000000L), // Aloe MMIO [ 0GB, 1GB)
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TLC = AddressSet.misaligned(0x60000000L, 0x20000000L) ++ // local memory behind L2 [1.5GB, 2GB)
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AddressSet.misaligned(0x80000000L, 0x2000000000L - 0x80000000L) ++ // Aloe DDR [ 2GB, 128GB)
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AddressSet.misaligned(0x3000000000L, 0x1000000000L), // local memory behind L2 [192GB, 256GB)
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syncTX = true
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)
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val localRoute = AddressSet.misaligned(0x40000000L, 0x20000000L) ++ // local MMIO [ 1GB, 1.5GB)
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AddressSet.misaligned(0x2000000000L, 0x1000000000L) // local MMIO [128GB, 192GB)
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val gpioParams = GPIOParams(address = BigInt(0x2400000000L), width = 4)
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// ChipLink skew RX clock
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val vc707_sys_clock_mmcm3 = Module(new vc707_sys_clock_mmcm3)
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//-----------------------------------------------------------------------
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// DUT
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//-----------------------------------------------------------------------
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// System runs at 100 MHz
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dut_clock := clk100
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dut_ndreset := !ereset_n // debug reset is external
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val ddr = IO(new XilinxVC707MIGPads(ddrParams))
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val pcie = IO(new XilinxVC707PCIeX1Pads)
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withClockAndReset(dut_clock, dut_reset) {
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val iofpga = Module(LazyModule(new IOFPGA(localRoute,ddrParams,chipLinkParams,gpioParams)).module)
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//---------------------------------------------------------------------
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// DDR
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//---------------------------------------------------------------------
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iofpga.io.xilinxvc707mig.sys_clk_i := sys_clock.asUInt
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mig_clock := iofpga.io.xilinxvc707mig.ui_clk
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mig_sys_reset := iofpga.io.xilinxvc707mig.ui_clk_sync_rst
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mig_mmcm_locked := iofpga.io.xilinxvc707mig.mmcm_locked
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iofpga.io.xilinxvc707mig.aresetn := mig_resetn
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iofpga.io.xilinxvc707mig.sys_rst := sys_reset
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ddr <> iofpga.io.xilinxvc707mig
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//---------------------------------------------------------------------
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// PCIe
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//---------------------------------------------------------------------
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iofpga.io.xilinxvc707pcie.axi_aresetn := pcie_dat_resetn
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pcie_dat_clock := iofpga.io.xilinxvc707pcie.axi_aclk_out
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pcie_cfg_clock := iofpga.io.xilinxvc707pcie.axi_ctl_aclk_out
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mmcm_lock_pcie := iofpga.io.xilinxvc707pcie.mmcm_lock
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iofpga.io.xilinxvc707pcie.axi_ctl_aresetn := pcie_dat_resetn
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pcie <> iofpga.io.xilinxvc707pcie
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//---------------------------------------------------------------------
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// ChipLink
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//---------------------------------------------------------------------
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chiplink <> iofpga.io.chiplink
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constrainChipLink(iofpga=true)
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chiplink.c2b.clk := clk100_180
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vc707_sys_clock_mmcm3.io.reset := reset
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vc707_sys_clock_mmcm3.io.clk_in1 := chiplink.b2c.clk.asUInt.toBool
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iofpga.io.chiplink.b2c.clk := vc707_sys_clock_mmcm3.io.clk_out1
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iofpga.io.rxlocked := vc707_sys_clock_mmcm3.io.locked
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//---------------------------------------------------------------------
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// GPIO
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//---------------------------------------------------------------------
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val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams))
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GPIOPinsFromPort(gpio_pins, iofpga.io.gpio)
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gpio_pins.pins.foreach { _.i.ival := Bool(false) }
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gpio_pins.pins.zipWithIndex.foreach {
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case(pin, idx) => led(idx) := pin.o.oval
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}
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// diagnostics
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led(4) := vc707_sys_clock_mmcm3.io.locked
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led(5) := ereset_n
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led(6) := iofpga.io.chiplink.b2c.send
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led(7) := iofpga.io.chiplink.c2b.send
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}
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}
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class IOFPGAConfig extends Config(new FreedomUVC707Config)
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