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  • 552553e526 Load 32 MiB bootimage from a 2048 sector offset (first partiton) ml507 Klemens Schölhorn 2018-06-13 00:34:19 +02:00
  • ee888b8c7b Rebuild when changing the bootloader Klemens Schölhorn 2018-06-13 00:33:46 +02:00
  • c812a8878f Properly set clock frequencies Klemens Schölhorn 2018-06-06 01:05:36 +02:00
  • 2c74ef7f03 Use correct frequency for the sd-spi interface Klemens Schölhorn 2018-05-19 19:04:56 +02:00
  • c27ee2215c Print everything send over serial to the terminal Klemens Schölhorn 2018-05-19 19:04:11 +02:00
  • ec4e3ec36d Use rocket config with fpu and mmu for booting linux Klemens Schölhorn 2018-05-19 19:00:57 +02:00
  • 5ed6fb3d37 TEST: Read 50 byte from sd card and write to terminal boot-test Klemens Schölhorn 2018-05-14 23:59:00 +02:00
  • 10c26c0f7b BOOT-TEST: Memory test, terminal writes, GPIO square wave Klemens Schölhorn 2018-04-19 01:35:02 +02:00
  • 87bb3a5f24 Use correct clock period and memory size in config Klemens Schölhorn 2018-05-14 20:10:08 +02:00
  • a3f166d5a2 Pull in memory and terminal improvements Klemens Schölhorn 2018-05-14 20:08:41 +02:00
  • 175ed051d3 Pull in the new XilinxML507MIGToTL implementation Klemens Schölhorn 2018-05-10 21:43:51 +02:00
  • 291a765b8d Switch to new XilinxML507MIG and connect top level signals Klemens Schölhorn 2018-05-10 00:37:00 +02:00
  • 7b46ed6b7c Move ml507 mig TL stub into fpga-shells Klemens Schölhorn 2018-05-09 23:22:53 +02:00
  • 0cb89fd675 Add fragmenter in front of TLMemoryML507 and implementation notes Klemens Schölhorn 2018-05-03 01:57:06 +02:00
  • 7a514c6477 Point all submodules to tiband Klemens Schölhorn 2018-05-01 00:14:53 +02:00
  • e57dfd0f63 Update rocket-chip to fix rom generation Klemens Schölhorn 2018-05-01 00:11:11 +02:00
  • df44d1a3bc Make DIP switches available as GPIO register Klemens Schölhorn 2018-05-01 00:09:14 +02:00
  • 4f950772a1 Use 80 MHz for rocket and 48 MHz for the terminal Klemens Schölhorn 2018-04-30 22:54:57 +02:00
  • 97eeb7af29 Add terminal peripheral (in same clock domain for now) Klemens Schölhorn 2018-04-30 00:53:12 +02:00
  • 1cb558d2ea ml507: Don't accept any messages in the stub memory slave Klemens Schölhorn 2018-04-24 00:50:13 +02:00
  • d749f87696 ml507: Remove redundant clock definition Klemens Schölhorn 2018-04-24 00:49:39 +02:00
  • c10d2378e7 Disable TLMonitors Klemens Schölhorn 2018-04-19 01:34:10 +02:00
  • 2b5509009c Increase gpio width to 8 Klemens Schölhorn 2018-04-19 01:33:24 +02:00
  • 06a623a05a Update to latest ml507 shell Klemens Schölhorn 2018-04-19 01:33:09 +02:00
  • 48f3a7e590 Reduce rocket to a single core Klemens Schölhorn 2018-04-18 00:28:01 +02:00
  • 7449f52b9a Update to latest ml507 shell Klemens Schölhorn 2018-04-18 00:27:45 +02:00
  • 212821fe4d Switch to the new ML507Shell Klemens Schölhorn 2018-04-12 00:47:42 +02:00
  • 8e4eaf6603 Add TLMemoryML507 stub and integration Klemens Schölhorn 2018-04-11 22:26:14 +02:00
  • 0134a8f4dc Remove vc707 memory interface from ml507 Klemens Schölhorn 2018-04-11 20:55:00 +02:00
  • 5fdadd244c Add makefile and config for the ml507 board Klemens Schölhorn 2018-03-21 01:31:56 +01:00
  • cd9a525a66 Merge pull request #50 from sifive/update_readme_vc707_vivado2016dot4 origin/master master Henry Styles 2018-04-06 10:55:00 -07:00
  • 0e77cb9d87 U500 VC707 FPGA Dev Kit : update required Vivado version from 2016.1 to 2016.4 to fix synthesis bug effecting debug module Henry Styles 2018-04-06 10:54:03 -07:00
  • c0a2869e56 Merge pull request #49 from sifive/update_vc707_sdboot Henry Styles 2018-04-05 22:13:22 -07:00
  • 0663bb7627 Correct GPIO/SPI/UART base addresse for vc707 sdboot Henry Styles 2018-04-05 22:11:39 -07:00
  • fff18810cd Merge pull request #48 from sifive/chiplink Wesley W. Terpstra 2018-03-22 20:38:30 -07:00
  • 41f29484fd iofpga: add a vc707 chiplink slave target Wesley W. Terpstra 2018-03-22 18:27:19 -07:00
  • ac070218d1 submodule: bump to master Wesley W. Terpstra 2018-03-22 18:18:28 -07:00
  • d3fa3c8652 build.sbt: update to rocket's scala version Wesley W. Terpstra 2018-03-22 18:10:19 -07:00
  • 9b3763ea92 Merge pull request #47 from sifive/bump-repos Wesley W. Terpstra 2018-03-10 00:55:11 -08:00
  • 1445a381a1 platforms: fixup to new package names Wesley W. Terpstra 2018-03-05 15:45:01 -08:00
  • 6c9b159659 submodules: bump again for the latest refactor Wesley W. Terpstra 2018-03-05 15:14:23 -08:00
  • c076d53fe9 fpga-shells: bump to fix timing closure Wesley W. Terpstra 2018-02-25 15:08:30 -08:00
  • 756e2e82a1 build: update all submodules to their current master Wesley W. Terpstra 2018-02-25 10:33:25 -08:00
  • 3cdb87e613 Merge pull request #44 from sifive/bump-sifive-blocks Megan Wachs 2017-11-22 13:42:22 -08:00
  • 03cbe72c3e bump sifive-blocks for GPIO IOF fix Megan Wachs 2017-11-22 12:26:49 -08:00
  • 5a1d816f48 Add links to some documents for E300 Arty Dev Kit (#41) Megan Wachs 2017-11-03 16:59:30 -07:00
  • 07c6e4abd4 Merge pull request #40 from sifive/bump Wesley W. Terpstra 2017-11-03 16:59:17 -07:00
  • e1673b8670 README: note the vivado version requirements Wesley W. Terpstra 2017-11-03 12:53:00 -07:00
  • 4297b22472 unleashed: build quad-core instead Wesley W. Terpstra 2017-11-02 15:32:31 -07:00
  • 9f0877fc85 sdboot: support SMP boot Wesley W. Terpstra 2017-11-03 11:42:52 -07:00
  • c965442560 u500: enable FPU; needed by linux Wesley W. Terpstra 2017-11-02 15:21:39 -07:00
  • 9cb03a3708 README: update location of built files Wesley W. Terpstra 2017-11-03 11:20:08 -07:00
  • 4eaac79ec2 freedom: bump submodules to their respective masters Wesley W. Terpstra 2017-11-02 14:43:04 -07:00
  • 22ee433699 README: Updates to build bootloaders Shreesha Srinath 2017-08-20 01:39:45 -07:00
  • ec70d85cbc Updates to Freedom SoCs Shreesha Srinath 2017-08-18 18:21:04 -07:00
  • f4375c2266 Add variable to control what program gets flashed to FPGA. Richard Xia 2016-12-08 12:14:17 -08:00
  • e95ae8aa31 README: our systems are untethered Wesley W. Terpstra 2016-12-01 14:06:37 -08:00
  • 62d4e3ee15 Merge pull request #6 from sifive/remove-consts-vh Richard Xia 2016-12-01 11:05:18 -08:00
  • db2128b4c2 Also remove unused .prm file from Makefile. Richard Xia 2016-11-30 15:00:50 -08:00
  • c14985f3a7 Remove verilog header files built from Chisel .prm file. Richard Xia 2016-11-30 14:30:05 -08:00
  • 275e2cd693 Merge pull request #4 from sifive/fix_u500vc707devkit_dot_img Henry Styles 2016-11-29 20:38:00 -08:00
  • 9fbf40da42 fix U500 BootROM image for SDBoot Henry Styles 2016-11-29 20:32:16 -08:00
  • bf34011c03 Use public accessible URL for submodules Olof Kindgren 2016-11-29 23:22:26 +01:00
  • 32556462d0 Add submodules. SiFive 2016-11-29 05:23:27 -08:00
  • 3cf8128a30 Initial commit. SiFive 2016-11-29 05:23:11 -08:00