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Code Issues Releases Activity

Use correct clock period and memory size in config

This commit is contained in:
Klemens Schölhorn 2018-05-14 20:10:08 +02:00
parent a3f166d5a2
commit 87bb3a5f24
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/unleashed/u500ml507devkit/Config.scala
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@ -45,10 +45,10 @@ class U500ML507DevKitConfig extends Config(
new U500ML507DevKitPeripherals ++
new FreedomUML507Config().alter((site,here,up) => {
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 60000000) // 60 MHz clock
case MemoryML507Key => XilinxML507MIGParams(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x40000000L)
case ExtMem => up(ExtMem).copy(size = 0x10000000L)
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
idcodePartNum = 0x000, // Decided to simplify.