sdboot: support SMP boot
This commit is contained in:
Wesley W. Terpstra
parent
c965442560
commit
9f0877fc85
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@ -1,13 +1,16 @@
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// See LICENSE for license details.
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#include <platform.h>
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#include <smp.h>
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#include "common.h"
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.section .text.init
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.option norvc
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.globl _prog_start
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_prog_start:
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smp_pause(s1, s2)
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li sp, (PAYLOAD_DEST + 0x7fff000)
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call main
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smp_resume(s1, s2)
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csrr a0, mhartid
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la a1, dtb
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li s1, PAYLOAD_DEST
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@ -0,0 +1,142 @@
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#ifndef SIFIVE_SMP
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#define SIFIVE_SMP
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#include "platform.h"
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// The maximum number of HARTs this code supports
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#ifndef MAX_HARTS
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#define MAX_HARTS 32
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#endif
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#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
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#define CLINT1_END_HART_IPI CLINT1_CTRL_ADDR + (MAX_HARTS*4)
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// The hart that non-SMP tests should run on
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#ifndef NONSMP_HART
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#define NONSMP_HART 0
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#endif
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/* If your test cannot handle multiple-threads, use this:
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* smp_disable(reg1)
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*/
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#define smp_disable(reg1, reg2) \
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csrr reg1, mhartid ;\
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li reg2, NONSMP_HART ;\
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beq reg1, reg2, hart0_entry ;\
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42: ;\
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wfi ;\
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j 42b ;\
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hart0_entry:
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/* If your test needs to temporarily block multiple-threads, do this:
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* smp_pause(reg1, reg2)
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* ... single-threaded work ...
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* smp_resume(reg1, reg2)
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* ... multi-threaded work ...
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*/
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#define smp_pause(reg1, reg2) \
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li reg2, 0x8 ;\
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csrw mie, reg2 ;\
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li reg1, NONSMP_HART ;\
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csrr reg2, mhartid ;\
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bne reg1, reg2, 42f
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#ifdef CLINT1_CTRL_ADDR
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// If a second CLINT exists, then make sure we:
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// 1) Trigger a software interrupt on all harts of both CLINTs.
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// 2) Locate your own hart's software interrupt pending register and clear it.
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// 3) Wait for all harts on both CLINTs to clear their software interrupt
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// pending register.
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// WARNING: This code makes these assumptions, which are only true for Fadu as
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// of now:
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// 1) hart0 uses CLINT0 at offset 0
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// 2) hart2 uses CLINT1 at offset 0
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// 3) hart3 uses CLINT1 at offset 1
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// 4) There are no other harts or CLINTs in the system.
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#define smp_resume(reg1, reg2) \
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/* Trigger software interrupt on CLINT0 */ \
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li reg1, CLINT_CTRL_ADDR ;\
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41: ;\
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li reg2, 1 ;\
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sw reg2, 0(reg1) ;\
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addi reg1, reg1, 4 ;\
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li reg2, CLINT_END_HART_IPI ;\
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blt reg1, reg2, 41b ;\
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/* Trigger software interrupt on CLINT1 */ \
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li reg1, CLINT1_CTRL_ADDR ;\
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41: ;\
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li reg2, 1 ;\
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sw reg2, 0(reg1) ;\
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addi reg1, reg1, 4 ;\
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li reg2, CLINT1_END_HART_IPI ;\
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blt reg1, reg2, 41b ;\
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/* Wait to receive software interrupt */ \
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42: ;\
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wfi ;\
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csrr reg2, mip ;\
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andi reg2, reg2, 0x8 ;\
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beqz reg2, 42b ;\
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/* Clear own software interrupt bit */ \
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csrr reg2, mhartid ;\
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bnez reg2, 41f; \
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/* hart0 case: Use CLINT0 */ \
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li reg1, CLINT_CTRL_ADDR ;\
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slli reg2, reg2, 2 ;\
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add reg2, reg2, reg1 ;\
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sw zero, 0(reg2) ;\
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j 42f; \
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41: \
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/* hart 2, 3 case: Use CLINT1 and remap hart IDs to 0 and 1 */ \
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li reg1, CLINT1_CTRL_ADDR ;\
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addi reg2, reg2, -2; \
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slli reg2, reg2, 2 ;\
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add reg2, reg2, reg1 ;\
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sw zero, 0(reg2) ; \
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42: \
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/* Wait for all software interrupt bits to be cleared on CLINT0 */ \
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li reg1, CLINT_CTRL_ADDR ;\
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41: ;\
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lw reg2, 0(reg1) ;\
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bnez reg2, 41b ;\
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addi reg1, reg1, 4 ;\
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li reg2, CLINT_END_HART_IPI ;\
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blt reg1, reg2, 41b; \
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/* Wait for all software interrupt bits to be cleared on CLINT1 */ \
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li reg1, CLINT1_CTRL_ADDR ;\
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41: ;\
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lw reg2, 0(reg1) ;\
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bnez reg2, 41b ;\
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addi reg1, reg1, 4 ;\
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li reg2, CLINT1_END_HART_IPI ;\
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blt reg1, reg2, 41b; \
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/* End smp_resume() */
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#else
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#define smp_resume(reg1, reg2) \
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li reg1, CLINT_CTRL_ADDR ;\
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41: ;\
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li reg2, 1 ;\
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sw reg2, 0(reg1) ;\
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addi reg1, reg1, 4 ;\
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li reg2, CLINT_END_HART_IPI ;\
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blt reg1, reg2, 41b ;\
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42: ;\
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wfi ;\
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csrr reg2, mip ;\
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andi reg2, reg2, 0x8 ;\
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beqz reg2, 42b ;\
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li reg1, CLINT_CTRL_ADDR ;\
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csrr reg2, mhartid ;\
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slli reg2, reg2, 2 ;\
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add reg2, reg2, reg1 ;\
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sw zero, 0(reg2) ;\
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41: ;\
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lw reg2, 0(reg1) ;\
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bnez reg2, 41b ;\
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addi reg1, reg1, 4 ;\
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li reg2, CLINT_END_HART_IPI ;\
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blt reg1, reg2, 41b
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#endif /* ifdef CLINT1_CTRL_ADDR */
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#endif
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