Add terminal peripheral (in same clock domain for now)
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Subproject commit b2b19cc82223703f72a4d98796e5cab0bd393d6d
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Subproject commit 9c06418352d41142bf91a6f5b8fa9a0aca87dddc
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@ -1 +1 @@
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Subproject commit 7ac56c01afed8044ab73d648a51966a7198af2c6
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Subproject commit d7b9834d96829575a84f83b48cacba7b6b3d9cbe
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@ -12,6 +12,7 @@ import freechips.rocketchip.tile._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.terminal._
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import sifive.freedom.unleashed.u500ml507devkit.fpga._
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@ -32,6 +33,8 @@ class U500ML507DevKitPeripherals extends Config((site, here, up) => {
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SPIParams(rAddress = BigInt(0x64001000L)))
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case PeripheryGPIOKey => List(
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GPIOParams(address = BigInt(0x64002000L), width = 8))
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case PeripheryTerminalKey =>
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TerminalParams(address = BigInt(0x64003000L))
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case PeripheryMaskROMKey => List(
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MaskROMParams(address = 0x10000, name = "BootROM"))
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})
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@ -41,6 +41,7 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
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// Connect peripherals
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//---------------------------------------------------------------------
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connectTerminal (dut)
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connectDebugJTAG(dut)
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connectSPI (dut)
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connectUART (dut)
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@ -13,6 +13,7 @@ import freechips.rocketchip.system._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.terminal._
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import sifive.freedom.unleashed.u500ml507devkit.fpga._
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@ -25,6 +26,7 @@ class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem
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with HasPeripheryDebug
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with HasSystemErrorSlave
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with HasPeripheryUART
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with HasPeripheryTerminal
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with HasPeripherySPI
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with HasPeripheryGPIO
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with HasMemoryML507 {
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@ -36,6 +38,7 @@ class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
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with HasRTCModuleImp
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with HasPeripheryDebugModuleImp
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with HasPeripheryUARTModuleImp
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with HasPeripheryTerminalModuleImp
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with HasPeripherySPIModuleImp
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with HasPeripheryGPIOModuleImp {
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// Reset vector is set to the location of the mask rom
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