riscv
/
freedom
1
0
Fork 0
Code Issues Releases Activity

Properly set clock frequencies

This commit is contained in:
Klemens Schölhorn 2018-06-06 01:05:36 +02:00
parent 2c74ef7f03
commit c812a8878f
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket-chip

@ -1 +1 @@
Subproject commit 81d631a6a1d9323f876b87e8af7f23042c33e3f0
Subproject commit 8710fe9561ba564379579c6d0dda951c25715d1b

2
src/main/scala/unleashed/u500ml507devkit/Config.scala
View File

@ -20,6 +20,7 @@ import sifive.fpgashells.devices.xilinx.xilinxml507mig._
class FreedomUML507Config extends Config(
new WithoutTLMonitors ++
new WithJtagDTM ++
new WithClockFrequency(60000000) ++ // 60 MHz
new WithNMemoryChannels(1) ++
new WithNSmallLinuxCores(1) ++
new BaseConfig
@ -45,7 +46,6 @@ class U500ML507DevKitConfig extends Config(
new U500ML507DevKitPeripherals ++
new FreedomUML507Config().alter((site,here,up) => {
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 60000000) // 60 MHz clock
case MemoryML507Key => XilinxML507MIGParams(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x10000000L)