Properly set clock frequencies
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Submodule rocket-chip updated: 81d631a6a1...8710fe9561
@ -20,6 +20,7 @@ import sifive.fpgashells.devices.xilinx.xilinxml507mig._
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class FreedomUML507Config extends Config(
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new WithoutTLMonitors ++
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new WithJtagDTM ++
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new WithClockFrequency(60000000) ++ // 60 MHz
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new WithNMemoryChannels(1) ++
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new WithNSmallLinuxCores(1) ++
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new BaseConfig
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@ -45,7 +46,6 @@ class U500ML507DevKitConfig extends Config(
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new U500ML507DevKitPeripherals ++
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new FreedomUML507Config().alter((site,here,up) => {
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case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
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case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 60000000) // 60 MHz clock
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case MemoryML507Key => XilinxML507MIGParams(address = Seq(AddressSet(0x80000000L,0x10000000L-1))) // 256 MiB
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case DTSTimebase => BigInt(1000000)
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case ExtMem => up(ExtMem).copy(size = 0x10000000L)
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