Henry Styles
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97e628639a
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Use a file instead of environment variable to pass VSRCS into Vivado
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2017-09-19 14:12:23 -07:00 |
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Henry Styles
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2bed0c30dc
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correct invoke of board specific ip.tcl
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2017-09-08 23:20:55 -07:00 |
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Henry Styles
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07b2ae07d2
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Merge pull request #4 from sifive/vc707_2GB
Support both 4G and 1GB DIMM configuration for VC707
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2017-09-08 16:09:18 -07:00 |
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Henry Styles
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9f75e6eb59
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Support both 4G and 1GB DIMM configuration for VC707
Generate IP TCL and MIG projects from the Chisel blackboxes
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2017-09-08 15:52:53 -07:00 |
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Megan Wachs
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e49f49686d
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Merge pull request #1 from sifive/synchronizers
synchronizers: Use new primitives
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2017-09-07 13:33:26 -07:00 |
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Megan Wachs
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31650a2d23
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Merge remote-tracking branch 'origin/master' into synchronizers
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2017-09-07 10:46:03 -07:00 |
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Henry Styles
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385ffa7d9a
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Merge pull request #3 from sifive/freedomu500vc707devkit_fix_xdc
fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
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2017-09-07 10:42:32 -07:00 |
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Henry Styles
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b7ee0ab0f0
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fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
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2017-09-07 10:41:12 -07:00 |
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Megan Wachs
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cab572fab2
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synchronizers: decided that ShiftRegInit should be reversed as the others.
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2017-09-07 09:54:35 -07:00 |
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Megan Wachs
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fd70d118d3
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synchronizers: Update constraints to match new hierarchy for synchronizers
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2017-09-07 07:50:22 -07:00 |
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Megan Wachs
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13671f906d
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synchronizers: Use new primitives
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2017-09-06 11:00:25 -07:00 |
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Shreesha Srinath
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2389e6e957
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Fix the package path for xilinx vc707mig
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2017-08-18 14:47:03 -07:00 |
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Shreesha Srinath
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38afe2957f
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Fixing typos in the tcl script
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2017-08-18 11:34:35 -07:00 |
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Shreesha Srinath
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ae767458af
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Pass debug hooks through project-specific makefiles
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2017-08-18 11:27:02 -07:00 |
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Shreesha Srinath
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c58e79f155
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vc707: Updates to the constraints and shell
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2017-08-17 18:51:01 -07:00 |
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Shreesha Srinath
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ab8cf0775f
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Initial commit for fpga-shells
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2017-08-16 11:23:45 -07:00 |
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