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79b53cf2ae
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Add dip switches and clean up top interface
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2018-05-01 00:07:58 +02:00 |
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5bcc4e82fd
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Generate separate processor and terminal clocks
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2018-04-30 22:52:02 +02:00 |
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9c06418352
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Add terminal/dvi io (unsing the same clock for now)
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2018-04-30 00:41:05 +02:00 |
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b2b19cc822
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Add clock and proper reset feedback to ml507
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2018-04-19 01:29:15 +02:00 |
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5db71d11c2
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Fix polarity of buttons and dips on the ml507
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2018-04-19 01:28:36 +02:00 |
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f4ae1d469f
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Remove unused signals (pcie, mem) from ml507 shell
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2018-04-19 01:27:35 +02:00 |
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0b421d5645
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Remove incorrect jtag pin constraints form ml507
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2018-04-19 01:26:15 +02:00 |
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8329b232e2
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Hold ml507 in reset while clock not locked
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2018-04-19 01:25:31 +02:00 |
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2ff28e6af6
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Add status indication led for the reset button
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2018-04-18 00:26:43 +02:00 |
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41362a1cb5
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Remove unused UART signals (rs and cs) from ml507
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2018-04-18 00:26:00 +02:00 |
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e9625bf8ee
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Add initial ML507Shell stub based on VC707Shell
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2018-04-12 00:42:46 +02:00 |
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Wesley W. Terpstra
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9d02f530fc
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vc707shell: work-around too many '++'s => stack overflow issue
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2018-03-22 18:08:32 -07:00 |
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Wesley W. Terpstra
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080119ec7a
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chiplink: add pinout (#20)
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2018-03-22 17:13:25 -07:00 |
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Henry Cook
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0ca9f2bb66
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periphery: bus api update (#17)
* periphery: bus api update
* Update XilinxVC707MIGPeriphery.scala
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2018-03-01 01:16:04 -08:00 |
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Wesley W. Terpstra
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8519ba8d4e
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vc707: setup 100MHz PLL
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2018-02-08 07:21:45 -08:00 |
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Wesley W. Terpstra
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9c38f20333
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vc707 axi: move addresses to line up with ChipLink
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2018-02-08 07:21:44 -08:00 |
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Henry Styles
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61ece0bf00
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VC707 Shell : additional skewed clocks
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2018-02-08 07:21:44 -08:00 |
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Henry Styles
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0fdbb778bf
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VC707 Shell : move DebugJTAG pins and connect function into a separate mix-in
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2018-02-08 07:21:44 -08:00 |
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Henry Styles
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045b290fbd
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VC707 JTAG support throught XM105 FMC or reuse of LCD header
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2018-02-08 07:21:44 -08:00 |
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Henry Styles
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f9dc552ddc
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Xilinx unisim typo
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2018-02-08 07:21:44 -08:00 |
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Henry Styles
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33c88b8cc4
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Move Xilinx unisims into separate file
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2018-02-08 07:21:44 -08:00 |
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Wesley W. Terpstra
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8b0d7ec91a
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TransferSizes: just because a device CAN do more does not mean it should (#15)
Capping TransferSizes at 128 fits nicely in 3 size bits.
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2017-12-10 00:42:11 -08:00 |
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Henry Styles
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e1bfb75188
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VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock
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2017-11-01 14:23:07 -07:00 |
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Wesley W. Terpstra
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df8e6b8e8c
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xilinxvc707pciex1: use new node-style API and abstract crossing (#13)
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2017-10-28 12:27:24 -07:00 |
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Wesley W. Terpstra
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65ac5d4588
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xilinxVC707mig: convert to the island pattern (#12)
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2017-10-26 16:38:52 -07:00 |
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Henry Styles
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61b167e8d9
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VC707 : use IO bundles directly from the PCIe and MIG devices instead of redeclaring signals
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2017-10-23 16:53:59 -07:00 |
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Wesley W. Terpstra
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d8e50c7646
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TLToAXI4: remove now unnecessary argument (#10)
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2017-10-12 14:37:21 -07:00 |
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Wesley W. Terpstra
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4af0552374
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diplomacy: update to new API (#7)
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2017-09-27 16:32:43 -07:00 |
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Megan Wachs
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bf48e2c7c4
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signal_bundles: Use the new way as .fromPorts is gone
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2017-09-22 13:31:11 -07:00 |
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Henry Styles
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9f75e6eb59
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Support both 4G and 1GB DIMM configuration for VC707
Generate IP TCL and MIG projects from the Chisel blackboxes
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2017-09-08 15:52:53 -07:00 |
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Megan Wachs
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13671f906d
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synchronizers: Use new primitives
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2017-09-06 11:00:25 -07:00 |
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Shreesha Srinath
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2389e6e957
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Fix the package path for xilinx vc707mig
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2017-08-18 14:47:03 -07:00 |
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Shreesha Srinath
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c58e79f155
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vc707: Updates to the constraints and shell
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2017-08-17 18:51:01 -07:00 |
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Shreesha Srinath
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ab8cf0775f
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Initial commit for fpga-shells
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2017-08-16 11:23:45 -07:00 |
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