| .. |
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amoalu.scala
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Extend AMOALU to support RV32
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2016-03-10 17:32:23 -08:00 |
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bram.scala
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move NastiROM and HastiRAM into rom.scala and bram.scala
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2016-05-06 11:31:22 -07:00 |
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broadcast.scala
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fix BroadcastHub allocation and routing
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2016-04-05 16:21:18 -07:00 |
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cache.scala
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don't add pending reads if data is already available
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2016-04-06 15:43:21 -07:00 |
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coherence.scala
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fix more Chisel3 deprecations
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2016-01-14 14:55:45 -08:00 |
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consts.scala
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Let isRead be true for store-conditional
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2015-09-25 15:28:02 -07:00 |
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converters.scala
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fix order of assignments in ManagerTileLinkNetworkPort
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2016-05-11 16:45:00 -07:00 |
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directory.scala
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First pages commit
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2015-04-29 13:18:26 -07:00 |
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dma.scala
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make sure CSR width is parameterizable
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2016-02-02 12:49:58 -08:00 |
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ecc.scala
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Chisel3 compatibility: use >>Int instead of >>UInt
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2015-08-04 13:15:17 -07:00 |
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htif.scala
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Take a stab at the PRCI-Rocket interface
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2016-05-02 15:20:33 -07:00 |
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interconnect.scala
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assert that TileLink router has valid route
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2016-05-03 12:18:06 -07:00 |
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metadata.scala
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Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.
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2016-03-10 17:14:34 -08:00 |
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network.scala
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Improve simulation speed of BasicCrossbar
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2016-04-01 13:28:11 -07:00 |
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package.scala
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First pages commit
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2015-04-29 13:18:26 -07:00 |
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plic.scala
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Improve PLIC QoR
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2016-05-10 17:03:56 -07:00 |
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prci.scala
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Add trivial version of PRCI block
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2016-05-02 17:49:10 -07:00 |
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rom.scala
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move NastiROM and HastiRAM into rom.scala and bram.scala
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2016-05-06 11:31:22 -07:00 |
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rtc.scala
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Add new RTC as TileLink slave, not AXI master
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2016-04-27 11:55:35 -07:00 |
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scr.scala
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print the base address of each SCR as indicated
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2016-04-28 16:31:56 +01:00 |
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tilelink.scala
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use manager_id instead of client_id in GrantFromSrc and FinishToDst
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2016-04-07 11:20:16 -07:00 |
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uncore.scala
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fix BroadcastHub allocation and routing
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2016-04-05 16:21:18 -07:00 |
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util.scala
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Chisel3 compatibility fix
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2016-03-10 17:32:23 -08:00 |
