110 lines
3.4 KiB
Scala
110 lines
3.4 KiB
Scala
package uncore
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import Chisel._
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import cde.{Parameters, Field}
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import junctions._
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class BRAMSlave(depth: Int)(implicit val p: Parameters) extends Module
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with HasTileLinkParameters {
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val io = new ClientUncachedTileLinkIO().flip
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val bram = SeqMem(depth, Bits(width = tlDataBits))
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val (s0_get :: s0_getblk :: s0_put :: s0_putblk :: Nil) = Seq(
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Acquire.getType, Acquire.getBlockType, Acquire.putType, Acquire.putBlockType
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).map(io.acquire.bits.isBuiltInType _)
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val fire_acq = io.acquire.fire()
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val fire_gnt = io.grant.fire()
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val multibeat = Reg(init = Bool(false))
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when (fire_acq) {
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multibeat := s0_getblk
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}
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val s0_valid = io.acquire.valid || multibeat
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val s1_valid = Reg(next = s0_valid, init = Bool(false))
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val s1_acq = RegEnable(io.acquire.bits, fire_acq)
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val s0_addr = Cat(io.acquire.bits.addr_block, io.acquire.bits.addr_beat)
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val s1_beat = s1_acq.addr_beat + Mux(io.grant.ready, UInt(1), UInt(0))
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val s1_addr = Cat(s1_acq.addr_block, s1_beat)
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val raddr = Mux(multibeat, s1_addr, s0_addr)
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val last = (s1_acq.addr_beat === UInt(tlDataBeats-1))
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val ren = (io.acquire.valid && (s0_get || s0_getblk)) || (multibeat && !last)
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val wen = (io.acquire.valid && (s0_put || s0_putblk))
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val rdata = bram.read(raddr, ren)
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val wdata = io.acquire.bits.data
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val wmask = io.acquire.bits.wmask()
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assert(!io.acquire.valid || wmask === Fill(tlDataBytes, Bool(true)),
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"bram: subblock writes not supported")
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when (wen) {
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bram.write(s0_addr, wdata)
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}
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when (multibeat && fire_gnt) {
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s1_acq.addr_beat := s1_beat
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when (last) {
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multibeat := Bool(false)
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}
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}
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io.grant.valid := s1_valid
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io.grant.bits := Grant(
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is_builtin_type = Bool(true),
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g_type = s1_acq.getBuiltInGrantType(),
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client_xact_id = s1_acq.client_xact_id,
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manager_xact_id = UInt(0),
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addr_beat = s1_acq.addr_beat,
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data = rdata)
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val stall = multibeat || (io.grant.valid && !io.grant.ready)
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io.acquire.ready := !stall
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}
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class HastiRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) {
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val io = new HastiSlaveIO
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val hastiDataBytes = hastiDataBits/8
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val wdata = Vec.tabulate(hastiDataBytes)(i => io.hwdata(8*(i+1)-1,8*i))
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val waddr = Reg(UInt(width = hastiAddrBits))
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val wvalid = Reg(init = Bool(false))
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val wsize = Reg(UInt(width = SZ_HSIZE))
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val ram = SeqMem(depth, Vec(hastiDataBytes, Bits(width = 8)))
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val max_wsize = log2Ceil(hastiDataBytes)
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val wmask_lut = MuxLookup(wsize, SInt(-1, hastiDataBytes).asUInt,
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(0 until max_wsize).map(1 << _).map(sz => (UInt(sz) -> UInt((1 << sz << sz) - 1))))
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val wmask = (wmask_lut << waddr(max_wsize - 1, 0))(hastiDataBytes - 1, 0)
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val is_trans = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ)
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val raddr = io.haddr >> UInt(2)
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val ren = is_trans && !io.hwrite
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val bypass = Reg(init = Bool(false))
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val last_wdata = Reg(next = wdata)
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val last_wmask = Reg(next = wmask)
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when (is_trans && io.hwrite) {
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waddr := io.haddr
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wsize := io.hsize
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wvalid := Bool(true)
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} .otherwise { wvalid := Bool(false) }
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when (ren) { bypass := wvalid && (waddr >> UInt(2)) === raddr }
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when (wvalid) {
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ram.write(waddr >> UInt(2), wdata, wmask.toBools)
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}
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val rdata = ram.read(raddr, ren)
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io.hrdata := Cat(rdata.zip(wmask.toBools).zip(wdata).map {
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case ((rbyte, wsel), wbyte) => Mux(wsel && bypass, wbyte, rbyte)
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}.reverse)
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io.hreadyout := Bool(true)
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io.hresp := HRESP_OKAY
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}
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