.. |
arbiter.scala
|
support memory transaction aborts
|
2012-03-06 00:35:02 -08:00 |
coherence.scala
|
fix coherence bug
|
2012-03-16 01:24:07 -07:00 |
consts.scala
|
now HAVE_VEC is true, since it passes the emulator
|
2012-03-19 03:10:00 -07:00 |
cpu.scala
|
add chosen
|
2012-03-18 20:43:17 -07:00 |
ctrl_util.scala
|
fixes to match verilog X semantics
|
2012-03-19 03:10:00 -07:00 |
ctrl_vec.scala
|
update vector fence names and encoding
|
2012-03-18 20:42:38 -07:00 |
ctrl.scala
|
fix id interrupt signal
|
2012-03-19 15:13:57 -07:00 |
divider.scala
|
change package name and sbt project name to rocket
|
2012-02-25 17:09:26 -08:00 |
dpath_alu.scala
|
clean up cache interfaces; avoid reserved keywords
|
2012-03-16 00:44:16 -07:00 |
dpath_util.scala
|
drop vec_irq_aux pcr register, now everything goes through badvaddr
|
2012-03-17 14:03:57 -07:00 |
dpath_vec.scala
|
changes to xcpt handling
|
2012-03-17 17:50:37 -07:00 |
dpath.scala
|
retime D$ bypass into beginning of EX stage
|
2012-03-16 18:35:54 -07:00 |
dtlb.scala
|
add pf fault handling
|
2012-03-18 15:06:39 -07:00 |
fpu.scala
|
fix signedness of zero fmul results
|
2012-03-10 00:21:51 -08:00 |
htif.scala
|
fix minor coherence bugs
|
2012-03-13 19:10:54 -07:00 |
icache_prefetch.scala
|
fix icache prefetch global_xact_id bug
|
2012-03-11 00:50:11 -08:00 |
icache.scala
|
icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data
|
2012-03-08 18:47:32 -08:00 |
instructions.scala
|
update vector fence names and encoding
|
2012-03-18 20:42:38 -07:00 |
itlb.scala
|
clean up priority encoders
|
2012-02-29 16:13:14 -08:00 |
multiplier.scala
|
clean up ioDecoupled/ioPipe interface
|
2012-03-01 20:48:46 -08:00 |
nbdcache.scala
|
fixes to match verilog X semantics
|
2012-03-19 03:10:00 -07:00 |
ptw.scala
|
hookup vitlb ptw port
|
2012-03-17 23:01:06 -07:00 |
queues.scala
|
support non-power-of-2 queue sizes
|
2012-03-13 01:58:28 -07:00 |
slowio.scala
|
use divided clk for htif. UDPATE YOUR FESVR
|
2012-03-15 18:36:51 -07:00 |
top.scala
|
use divided clk for htif. UDPATE YOUR FESVR
|
2012-03-15 18:36:51 -07:00 |
util.scala
|
fix RRArbiter
|
2012-03-19 00:19:33 -07:00 |