riscv
/
rocket-chip
1
0
Fork 0
Code Releases Activity

Commit Graph

  • 91c252ad08 fixing output enable signals for data/tag SRAMs Rimas Avizienis 2011-11-12 15:47:47 -0800
  • 83d90c4dab more itlb/dtlb/ptw fixes Rimas Avizienis 2011-11-12 15:00:45 -0800
  • 73416f224b more tlb/ptw debugging Rimas Avizienis 2011-11-12 00:25:06 -0800
  • 44926866b7 updated itlb Rimas Avizienis 2011-11-11 18:48:34 -0800
  • a1ce908541 dcache/dtlb overhaul Rimas Avizienis 2011-11-11 18:18:47 -0800
  • e4fa94aa27 checkpoint Rimas Avizienis 2011-11-10 17:41:22 -0800
  • f86d5b1334 cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB Rimas Avizienis 2011-11-10 11:26:13 -0800
  • 4bd0263a4a added misaligned instruction check, cleaned up badvaddr handling Rimas Avizienis 2011-11-10 03:38:59 -0800
  • 603ede8bfe access faults now write badvaddr PCR register with faulting address Rimas Avizienis 2011-11-10 02:46:09 -0800
  • 36aa4bcc9d moved exception handling from ex stage in dpath to mem stage in ctrl Rimas Avizienis 2011-11-10 00:50:09 -0800
  • fbfa356d2a fixed eret instruction Rimas Avizienis 2011-11-10 00:37:00 -0800
  • 62407b4668 more tlb/ptw fixes Rimas Avizienis 2011-11-10 00:23:29 -0800
  • 6664af3bc0 cleanup before adding dtlb Rimas Avizienis 2011-11-09 23:27:29 -0800
  • 9aca403aa8 more itlb integration & cleanup Rimas Avizienis 2011-11-09 23:18:14 -0800
  • c29d2821b4 cleanup, fixes, initial commit for dtlb.scala Rimas Avizienis 2011-11-09 21:54:11 -0800
  • e96430d862 integrating ITLB & PTW Rimas Avizienis 2011-11-09 14:52:17 -0800
  • 7130edac8d fix for flushed div/mul instructions Rimas Avizienis 2011-11-07 01:03:47 -0800
  • 9d63087eb2 changed caches to use separate sram modules for tag and data arrays Rimas Avizienis 2011-11-07 00:58:25 -0800
  • 4d64099103 cleanup Rimas Avizienis 2011-11-04 20:52:21 -0700
  • 2db9ee12bc fixed eret instruction, hello world runs Rimas Avizienis 2011-11-04 15:57:08 -0700
  • 4459935554 dcache fixes - all tests and ubmarks pass, hello world still broken Rimas Avizienis 2011-11-04 15:40:41 -0700
  • 3a02028a35 fixes to exception and dcache miss/blocked handling Rimas Avizienis 2011-11-02 13:32:32 -0700
  • 7a528d6255 fixes for div/mul hazard checking + cleanup Rimas Avizienis 2011-11-01 23:14:34 -0700
  • d8ffecf565 dcache fix Rimas Avizienis 2011-11-01 22:10:06 -0700
  • 7479e085ec dcache loads working - 1/2 cycle load/use delay depending on load type Rimas Avizienis 2011-11-01 22:04:45 -0700
  • 3b3d988fde dcache loads working - 1/2 cycle load/use delay depending on load type Rimas Avizienis 2011-11-01 21:25:52 -0700
  • 2b67eee683 pipeline changes for replay on dcache miss Rimas Avizienis 2011-11-01 19:05:27 -0700
  • 08b89e7710 interface cleanup, major pipeline changes Rimas Avizienis 2011-11-01 17:59:27 -0700
  • ace4c9d13c dcache fixes Rimas Avizienis 2011-10-31 17:17:36 -0700
  • 65f8b2461c dcache tweaks Rimas Avizienis 2011-10-31 16:47:31 -0700
  • 172e561a78 added once cycle latency store pipelined d$ Rimas Avizienis 2011-10-31 15:37:37 -0700
  • c06e2d16e4 initial commit of rocket chisel project, riscv assembly tests and benchmarks Rimas Avizienis 2011-10-25 23:02:47 -0700