dcache fixes
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@ -321,9 +321,9 @@ class rocketDCacheDM_1C(lines: Int, addrbits: Int) extends Component {
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when (tag_we && req_flush) {
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vb_array <== vb_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(0,1));
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}
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val tag_valid = vb_rdata.toBool;
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val tag_match = tag_valid && !req_flush && (tag_rdata === r_cpu_req_addr(tagmsb, taglsb));
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val tag_match = tag_valid && (tag_rdata === r_cpu_req_addr(tagmsb, taglsb));
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when ((state === s_ready) && r_cpu_req_val && req_store) {
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p_store_data <== r_cpu_req_data;
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@ -333,7 +333,7 @@ class rocketDCacheDM_1C(lines: Int, addrbits: Int) extends Component {
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}
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val addr_match = (r_cpu_req_addr(tagmsb, offsetlsb) === p_store_addr(tagmsb, offsetlsb));
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val drain_store = ((state === s_ready) && p_store_valid && (!r_cpu_req_val || !req_load || addr_match))
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val drain_store = ((state === s_ready) && p_store_valid && (!r_cpu_req_val || !tag_match || !req_load || addr_match))
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val resolve_store = (state === s_resolve_miss) && req_store;
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val do_store = drain_store | resolve_store;
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@ -389,7 +389,7 @@ class rocketDCacheDM_1C(lines: Int, addrbits: Int) extends Component {
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val ldst_conflict = r_cpu_req_val && req_load && p_store_valid && addr_match;
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// output signals
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io.cpu.req_rdy := (state === s_ready) && !ldst_conflict && (!r_cpu_req_val || tag_match);
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io.cpu.req_rdy := (state === s_ready) && !ldst_conflict && (!r_cpu_req_val || (tag_match && !req_flush));
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io.cpu.resp_val := ((state === s_ready) && r_cpu_req_val && tag_match && req_load && !(p_store_valid && addr_match)) ||
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((state === s_resolve_miss) && req_flush);
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@ -400,11 +400,11 @@ class rocketDCacheDM_1C(lines: Int, addrbits: Int) extends Component {
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Mux(r_cpu_req_addr(offsetlsb).toBool, data_array_rdata(127, 64),
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data_array_rdata(63,0));
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io.mem.req_val := (state === s_req_refill) || (state === s_writeback);
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io.mem.req_rw := (state === s_writeback);
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io.mem.req_val := (state === s_req_refill) || (state === s_writeback);
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io.mem.req_rw := (state === s_writeback);
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io.mem.req_wdata := data_array_rdata;
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io.mem.req_tag := UFix(0);
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io.mem.req_addr :=
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io.mem.req_tag := UFix(0);
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io.mem.req_addr :=
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Mux(state === s_writeback, Cat(tag_rdata, r_cpu_req_addr(indexmsb, indexlsb), rr_count).toUFix,
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Cat(r_cpu_req_addr(tagmsb, indexlsb), Bits(0,2)).toUFix);
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