riscv/rocket-chip
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  • 8b908465e0 [tl2] convert NBDcache to TL2 (WIP; compiles but untested) Henry Cook 2016-11-18 19:01:36 -0800
  • 5f1cc19d71 [tl2] fix comment explaining permissions Henry Cook 2016-11-18 10:08:39 -0800
  • 10112da4e7 [tl2] won't need putthrough opcode Henry Cook 2016-11-18 10:03:29 -0800
  • 001d9821bd Merge remote-tracking branch 'origin/master' into tl2-tile Wesley W. Terpstra 2016-11-18 18:19:31 -0800
  • 5b594ced29 Plic: support 0 interrupts gracefully Wesley W. Terpstra 2016-11-18 18:07:44 -0800
  • 13ec3853ed junctions: get unit tests running again Wesley W. Terpstra 2016-11-18 17:38:46 -0800
  • 10dd6070ad groundtest: gracefully handle zero uncached ports Wesley W. Terpstra 2016-11-18 17:26:28 -0800
  • 03bca77b33 tilelink2 Metadata: cannot assert data good when !valid Wesley W. Terpstra 2016-11-18 17:16:12 -0800
  • be8121eeaf coreplex: fix clock crossing Wesley W. Terpstra 2016-11-18 17:15:57 -0800
  • 0082d713af coreplex: disable Stateless config until we implement adapter Wesley W. Terpstra 2016-11-18 16:23:16 -0800
  • 8059d33217 groundtest: simplify FancyMemtestConfig for now Wesley W. Terpstra 2016-11-18 16:17:28 -0800
  • 04b9a68ea6 MergedPutRegression: wait for all Puts if tlMaxClientXacts != 3 Wesley W. Terpstra 2016-11-18 16:15:02 -0800
  • cd19bf65b8 regression: fix bad regression that deadlocks SoC with illegal D stall Wesley W. Terpstra 2016-11-18 15:45:52 -0800
  • 5f7fa3dae5 regression: remove illegal test which reuses the same ID Wesley W. Terpstra 2016-11-18 15:44:20 -0800
  • a6188efc41 rocketchip: break infinite Config loops Wesley W. Terpstra 2016-11-18 12:52:36 -0800
  • 37a3c22639 rocketchip: move from using cde to config Wesley W. Terpstra 2016-11-18 14:05:14 -0800
  • 40daea2e15 util: Config scheme supporting up with ++ Wesley W. Terpstra 2016-11-18 14:03:07 -0800
  • e5febcfa33 rocketchip: there are no more useful parameters to dump Wesley W. Terpstra 2016-11-18 14:10:47 -0800
  • 30425d1665 rocketchip: eliminate all Knobs Wesley W. Terpstra 2016-11-18 12:02:33 -0800
  • 119ccae9af rocketchip: don't use explicit cde namespace Wesley W. Terpstra 2016-11-18 12:32:49 -0800
  • 87cbd5c893 Merge pull request #439 from ucb-bar/add-chip-configs Richard Xia 2016-11-18 12:12:50 -0800
  • bab504cc3f Add various granular and composable configs. Richard Xia 2016-11-18 10:49:42 -0800
  • 5bd343bac8 [rocket] d_last && d.fire() => d_done Henry Cook 2016-11-17 15:53:46 -0800
  • 1ddccb1b33 [rocket] add TODO for single cycle ack Henry Cook 2016-11-17 15:48:33 -0800
  • 94086f2270 [tl2] broadcast hub probe port width bugfix Henry Cook 2016-11-17 13:51:25 -0800
  • 960c2723ab [tl2] MemoryOpCategories: use def to supply Cat'd consts Henry Cook 2016-11-17 11:06:05 -0800
  • 179c93db42 tilelink2 broadcast: make it controlled via Config Wesley W. Terpstra 2016-11-17 17:26:49 -0800
  • f4ca5ea1f3 rocketchip: match simulated memory width to ExtMem.beatBytes Wesley W. Terpstra 2016-11-17 15:38:11 -0800
  • 12d0d8bea2 rocketchip: remove obsolete bus configuration Wesley W. Terpstra 2016-11-17 14:30:15 -0800
  • c82b371354 rocketchip: remove obsolete TL1 config Wesley W. Terpstra 2016-11-17 14:24:45 -0800
  • dfc3a0dafb tilelink2: do not depend on obsolete TL1 configuration Wesley W. Terpstra 2016-11-17 14:07:53 -0800
  • 8a0ecdaaad groundtest: ComparatorConfig lives again Wesley W. Terpstra 2016-11-17 11:07:49 -0800
  • 92e233d596 [groundtest] testramaddr constant in package Henry Cook 2016-11-16 18:42:56 -0800
  • e1992d7c55 [rocket] grant addr bugfix Henry Cook 2016-11-16 18:12:06 -0800
  • 84f249bd03 [rocketchip] BigInt cast Henry Cook 2016-11-16 18:11:06 -0800
  • da7ecfd189 [rocket] probeack vs probeackdata bugfix Henry Cook 2016-11-16 17:27:02 -0800
  • 75d4347192 [groundtest] runs tests with new coreplex and top Henry Cook 2016-11-16 17:05:53 -0800
  • 24e3216fcf coreplex: allow zero interrupt sink/sources Henry Cook 2016-11-16 16:49:10 -0800
  • 479bc82f03 tilelink2 Broadcast: improve bufferless throughput Henry Cook 2016-11-16 16:17:06 -0800
  • 408e78e35e rocketchip Periphery: ExtMem and ExtBus Configs Henry Cook 2016-11-16 16:16:08 -0800
  • 1f51564577 [rocket] dcache probe ack data bugfix Henry Cook 2016-11-16 14:25:21 -0800
  • 66a2c5544e [rocket] L1D acquire addr bugfix Henry Cook 2016-11-16 13:14:43 -0800
  • c5e03c9c76 [rocket] dcache release addr bugfix Henry Cook 2016-11-16 12:53:20 -0800
  • 81d98304dc Merge pull request #438 from ucb-bar/bump-riscv-tools-for-riscv-test-updates Richard Xia 2016-11-16 12:26:48 -0800
  • 06a7b95d0d tilelink2 broadcast: support bufferless Config Wesley W. Terpstra 2016-11-16 12:25:11 -0800
  • 3703ed39f7 groundtest: PTW needs atomics Wesley W. Terpstra 2016-11-16 12:16:54 -0800
  • 5d2e637a4a tilelink2 Legacy: uncached TL never needs manager_xact_id Wesley W. Terpstra 2016-11-16 12:16:25 -0800
  • 6e5dd45f9a Bump riscv-tools to bump riscv-tests to pull in OpenOCD port randomization fix. Richard Xia 2016-11-16 11:33:15 -0800
  • 10e459fedb rocket: change connection between rocketchip and coreplex Wesley W. Terpstra 2016-11-15 18:27:52 -0800
  • 2d68f12115 [tl2] give groundtest tile some output nodes Henry Cook 2016-11-14 18:09:17 -0800
  • ab3dafb8bc Monitor: restore Probe&Acquire checks Wesley W. Terpstra 2016-11-14 15:36:52 -0800
  • 385b5d5698 axi4: default should be GET_EFFECTS Wesley W. Terpstra 2016-11-14 15:19:39 -0800
  • 0e30364f56 WIP Henry Cook 2016-11-14 13:39:01 -0800
  • c0efd247b0 [tl2] expand firstlast api and L1WB bugfix Henry Cook 2016-11-14 11:56:48 -0800
  • b7730d66f2 WIP bugfixes: run until corrupted WB data (beats repeated) Henry Cook 2016-11-11 18:34:48 -0800
  • 71315d5cf5 WIP scala compile and firrtl elaborate; monitor error Henry Cook 2016-11-11 13:07:45 -0800
  • afa1a6d549 WIP uncore and rocket changes compile Henry Cook 2016-11-10 15:56:42 -0800
  • 32fd11935c rocketchip: use TL2 and AXI4 for memory subsytem Wesley W. Terpstra 2016-11-03 21:31:26 -0700
  • 9d77e34bee tilelink2 Filter: make transfer cap robust against large filters Wesley W. Terpstra 2016-11-04 12:08:56 -0700
  • 4a2cf6431b coreplex: make 'mem' port an Option until we can use a Seq Wesley W. Terpstra 2016-11-04 12:14:28 -0700
  • 8f757a9135 coreplex: rename BankedL2 trait to BankedL2CoherenceManagers Wesley W. Terpstra 2016-11-04 11:51:59 -0700
  • b8df59f43b tilelink2 Broadcast: support "bufferless" implementation Wesley W. Terpstra 2016-11-04 11:32:15 -0700
  • 14800f8fb4 tilelink2 Broadcast: only support caching readable devices Wesley W. Terpstra 2016-11-04 11:20:37 -0700
  • d03046d11c coreplex: fix BankedL2 line width Wesley W. Terpstra 2016-11-04 11:18:31 -0700
  • ea602790a8 Merge pull request #432 from ucb-bar/tl2-address-filtering Wesley W. Terpstra 2016-11-04 00:12:43 -0700
  • da3cc3b299 coreplex: TileLink2 l1tol2 memory channels Wesley W. Terpstra 2016-11-03 19:48:05 -0700
  • 0f3947bb86 tilelink2 Broadcast: add special case handling for 0 cached clients Wesley W. Terpstra 2016-11-03 21:55:54 -0700
  • ba3c83287f tilelink2 Xbar: merge the AddressSets of fractured managers Wesley W. Terpstra 2016-11-03 19:05:53 -0700
  • 55326c29bb tilelink2: Filter adapter removes some of the address space Wesley W. Terpstra 2016-11-03 19:05:22 -0700
  • 163b7577bd Merge pull request #431 from ucb-bar/tl2-broadcast Wesley W. Terpstra 2016-11-03 15:39:43 -0700
  • 86ba94781b tilelink2: broadcast coherence manager Wesley W. Terpstra 2016-11-02 21:37:30 -0700
  • d067e87a7d tilelink2 Parameters: sinkId is per port, not per manager Wesley W. Terpstra 2016-11-02 17:53:32 -0700
  • 1b016051e8 Merge pull request #424 from ucb-bar/coreplex-cake Wesley W. Terpstra 2016-10-31 16:49:27 -0700
  • ed4224dde4 tilelink2 AtomicAutomata: fix AccessAck on same cycle as PutFull Wesley W. Terpstra 2016-10-31 15:17:10 -0700
  • f83d1d0aaf coreplex: rename trait CoreplexRISCVPlatform Wesley W. Terpstra 2016-10-31 11:40:33 -0700
  • f943c5d6ef rocketchip: connect rtcTick to coreplex Wesley W. Terpstra 2016-10-29 13:13:11 -0700
  • 4a0b29850c coreplex: reattach clint interrupt Wesley W. Terpstra 2016-10-29 12:39:37 -0700
  • a12fea51e8 Plic: skip reserved interrupt in interrupt map printout Wesley W. Terpstra 2016-10-29 12:39:04 -0700
  • aabd17d935 rocketchip: must create bundles within Module scope Wesley W. Terpstra 2016-10-29 03:30:49 -0700
  • d52615c39e coreplex: one IntNode per tile Wesley W. Terpstra 2016-10-29 01:30:11 -0700
  • e97844f71e coreplex: make it possible to override the ConfigString Wesley W. Terpstra 2016-10-29 01:19:16 -0700
  • 4de1822470 rocketchip: avoid using the nearly defunct GlobalAddrMap Wesley W. Terpstra 2016-10-29 00:25:58 -0700
  • 688e1bffdf rocketchip: pull rtcTick out of the coreplex Wesley W. Terpstra 2016-10-28 22:37:46 -0700
  • 5bca13ebdb rocketchip: use self-type constraints Wesley W. Terpstra 2016-10-28 22:30:13 -0700
  • d51b0b5c02 rocketchip: use self-type Wesley W. Terpstra 2016-10-28 21:56:11 -0700
  • 841a31479a coreplex: fix TinyConfig Wesley W. Terpstra 2016-10-28 21:34:04 -0700
  • ba529c3716 rocketchip: use TileLink2 interrupts Wesley W. Terpstra 2016-10-28 21:20:49 -0700
  • 6505431eac coreplex: use self-type constraints Wesley W. Terpstra 2016-10-28 18:37:24 -0700
  • ac886026e6 rocketchip: reduce number of type parameters Wesley W. Terpstra 2016-10-28 16:47:20 -0700
  • 043ed48c8c tilelink2 HintHandler: delay answers to help TL1 legacy clients Wesley W. Terpstra 2016-10-28 15:07:35 -0700
  • 72a7948ad2 rocketchip Periphery: move atomics before WidthWidget => 64-bit AMOs Wesley W. Terpstra 2016-10-28 15:05:49 -0700
  • 015c3b862a diplomacy: print out bus widths on edges in agent graph Wesley W. Terpstra 2016-10-28 14:00:55 -0700
  • 92ee498521 rocket scratchpad: support atomics Wesley W. Terpstra 2016-10-28 12:13:01 -0700
  • 0cc00e7616 regressions: test scratchpad Wesley W. Terpstra 2016-10-27 22:27:43 -0700
  • d2e9fa8ec6 Plic: remove path from ready to bits Wesley W. Terpstra 2016-10-27 21:35:16 -0700
  • 545154c1c3 groundtest: make it happy with TL2 addressing Wesley W. Terpstra 2016-10-27 19:55:40 -0700
  • 9a26cb7ec7 Debug: mark the debug device executable Wesley W. Terpstra 2016-10-27 18:38:14 -0700
  • e9725aea2f rocketchip: all of the address map now comes from TL2 Wesley W. Terpstra 2016-10-27 18:29:16 -0700
  • 401fd378b4 rocketchip: include devices from cbus in ConfigString Wesley W. Terpstra 2016-10-27 18:03:43 -0700
  • b68bc449e7 rocket: put a Fragmenter infront of the scratchpad Wesley W. Terpstra 2016-10-27 15:46:57 -0700