riscv/rocket-chip
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  • e31b84af33 axi4: use common BufferParams Wesley W. Terpstra 2017-03-16 15:32:17 -07:00
  • ca2c709d29 TLBuffer: move TLBufferParams to diplomacy.BufferParams Wesley W. Terpstra 2017-03-16 15:19:36 -07:00
  • 778c8a5c97 ToAHB: appease AHB VIP Wesley W. Terpstra 2017-03-16 15:17:05 -07:00
  • 963d244094 unittest: try both aFlow settings of TLToAHB Wesley W. Terpstra 2017-03-16 15:13:57 -07:00
  • 604a164b97 TLToAHB: rename parameter to aFlow Wesley W. Terpstra 2017-03-16 15:10:54 -07:00
  • bb49575368 ahb: rewrote TLToAHB to avoid retracting requests on stall Wesley W. Terpstra 2017-03-16 14:36:30 -07:00
  • 4f5f686c7e bump riscv-tools (#586) Henry Cook 2017-03-15 18:09:26 -07:00
  • 625919722c Merge pull request #584 from ucb-bar/ahb-in Wesley W. Terpstra 2017-03-14 19:28:09 -07:00
  • c95c2ca9c8 AHB: include bridge unit tests Wesley W. Terpstra 2017-03-13 16:24:57 -07:00
  • 0c5fd76089 ahb: implement a ToTL bridge Wesley W. Terpstra 2017-03-13 15:06:51 -07:00
  • 7f71df0925 apb: better test coverage Wesley W. Terpstra 2017-03-14 10:28:52 -07:00
  • 5885bf29b5 axi4: improve test harness Wesley W. Terpstra 2017-03-13 16:09:42 -07:00
  • d98fd942f1 tilelink2: optimize the supportsX check circuits Wesley W. Terpstra 2017-03-14 17:37:41 -07:00
  • 3c5c877409 tilelink2: make TLBuffer API more flexible Wesley W. Terpstra 2017-03-13 19:55:27 -07:00
  • 6fc3ec3d63 tileink2: add a TestRAM; a zero-delay RAM useful for testing Wesley W. Terpstra 2017-03-13 16:03:21 -07:00
  • e9c694522b Merge pull request #578 from ucb-bar/priv-1.10 Henry Cook 2017-03-14 13:20:19 -07:00
  • bb0390630c Merge branch 'master' into priv-1.10 Henry Cook 2017-03-13 21:40:12 -07:00
  • 1322a02637 Fixed Hasti can't handle N masters to one slave #571 (#576) Leway Colin 2017-03-14 11:36:53 +08:00
  • 4eb261c895 Merge pull request #582 from ucb-bar/more-fuzzing Henry Cook 2017-03-13 15:31:51 -07:00
  • d6f571cbbb Implement mstatus.TSR Andrew Waterman 2017-03-13 14:49:46 -07:00
  • 1fea0460ba Support superpage entries in TLB Andrew Waterman 2017-03-12 20:42:51 -07:00
  • 2d267b4940 Support corner cases in TLBPermissions Andrew Waterman 2017-03-11 19:29:25 -08:00
  • 90b5cc96cb Gracefully handle empty ports in AddressDecoder Andrew Waterman 2017-03-11 19:28:59 -08:00
  • c847559853 TLB: add a helper API to determine homogeneous page permissions Wesley W. Terpstra 2017-03-10 15:13:17 -08:00
  • eaf474a081 LFSR: use random intial value of the start register Wesley W. Terpstra 2017-03-13 13:16:17 -07:00
  • fe287864ef bump firrtl Henry Cook 2017-03-13 13:13:30 -07:00
  • 1a3fec61c0 Merge branch 'master' into priv-1.10 Henry Cook 2017-03-13 11:59:18 -07:00
  • d2da33e4b1 Fuzzer: use different LFSR seeds based on simulator seed Wesley W. Terpstra 2017-03-11 02:53:11 -08:00
  • bb6108abd5 Tests: include more random delays Wesley W. Terpstra 2017-03-10 17:10:41 -08:00
  • 0c7fb87390 TLDelayer: insert noise on invalid cycles Wesley W. Terpstra 2017-03-10 16:48:57 -08:00
  • 1c6dde8c15 Make parameters for TLToAHB and TLToAXI4 accessable (#581) Jacob Chang 2017-03-10 22:26:38 -08:00
  • dbc8f4b30b last => done Henry Cook 2017-03-09 18:56:54 -08:00
  • 380c10f7bd Zap conflicting TLB entries, preparing for superpage support Andrew Waterman 2017-03-10 14:00:36 -08:00
  • b24c43badb Don't double-count release traffic in perfctrs Andrew Waterman 2017-03-09 16:49:02 -08:00
  • 63f8ce36f6 Avoid VM exceptions in groundtest by setting Accessed bit Andrew Waterman 2017-03-09 16:48:28 -08:00
  • 4f8f05d635 Add performance counter facility Andrew Waterman 2017-03-09 00:28:19 -08:00
  • e57ee2692d bump tools Andrew Waterman 2017-03-09 12:46:39 -08:00
  • 33b6d48376 Fix haltnot reporting (previously always returned 0) Andrew Waterman 2017-03-09 12:37:20 -08:00
  • 24a2278fc4 Perform all illegal-instruction detection in ID stage Andrew Waterman 2017-03-07 14:33:51 -08:00
  • 7668827741 Support unrolling the integer divider Andrew Waterman 2017-03-06 15:03:14 -08:00
  • 74d8d672bf Improve BTB critical path at slight accuracy cost Andrew Waterman 2017-03-05 23:01:07 -08:00
  • 11c8857b5d Don't re-read I$ RAMs on stall Andrew Waterman 2017-03-05 21:43:20 -08:00
  • db0a02b78e WIP on priv-1.10 Andrew Waterman 2017-02-27 14:27:19 -08:00
  • 43dea38ee9 dcache: we need the bits within the beat so select the right word (#575) Wesley W. Terpstra 2017-03-08 00:19:09 -08:00
  • 603b8af2eb Don't canonicalize 32-bit FP results in the various pipelines Andrew Waterman 2017-03-07 17:26:09 -08:00
  • f505aba1ac Use sNaN value for flw, like other single-precision ops Andrew Waterman 2017-03-07 17:25:19 -08:00
  • cc389bea90 Fix in-register representation of fdiv.s/fsqrt.s result Andrew Waterman 2017-03-07 17:23:06 -08:00
  • 4af437fdab RANDOMIZE_MEM_INIT vlsi_mem_gen (#572) Henry Cook 2017-03-07 01:56:15 -08:00
  • d0ae087587 rocket: allow scratchpad address to be configurable (#570) Henry Cook 2017-03-06 21:35:45 -08:00
  • 229fb2251d coreplex: hack to fix tile dedup (#569) Henry Cook 2017-03-06 16:36:03 -08:00
  • 33ffb62326 Merge pull request #568 from ucb-bar/elide-empty-int-ext Henry Cook 2017-03-03 12:46:11 -08:00
  • 676974281a rocket: describe dcache scratchpad as memory Wesley W. Terpstra 2017-03-03 02:54:48 -08:00
  • 1eeaa390c6 diplomacy: output JSON formatted version of DTS Wesley W. Terpstra 2017-03-03 02:45:11 -08:00
  • 0178248551 diplomacy: evaluate ResourceBindings only once Wesley W. Terpstra 2017-03-03 02:04:17 -08:00
  • 8e4f348dda rocket: if no MMU, don't print it in DTS Wesley W. Terpstra 2017-03-03 00:48:26 -08:00
  • 7660be039c rocketchip: add WithTimebase to set RTC frequency Wesley W. Terpstra 2017-03-03 00:47:50 -08:00
  • 57a329408c PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0 Wesley W. Terpstra 2017-03-03 00:28:55 -08:00
  • 46369850cf Merge pull request #567 from ucb-bar/dts Wesley W. Terpstra 2017-03-02 21:51:51 -08:00
  • 4535de2669 rocket: use diplomatic interrupts Wesley W. Terpstra 2017-03-02 13:37:25 -08:00
  • d3c5318714 build: remove the now obsolete config string Wesley W. Terpstra 2017-03-02 11:02:35 -08:00
  • 93ca555c20 IntXing: support configurable sync depth Wesley W. Terpstra 2017-03-02 13:33:05 -08:00
  • 637bc6c3a7 coreplex: pretty print discontiguous ranges properly Wesley W. Terpstra 2017-03-02 13:32:42 -08:00
  • 7ff9f88ad7 rocket: connect interrupt map for Plic+Clint Wesley W. Terpstra 2017-03-01 21:57:00 -08:00
  • 38489ad9b0 tilelink2: bring IntNode parameters up to the current standard Wesley W. Terpstra 2017-03-01 18:23:28 -08:00
  • 5bd9f18e5b rocket: add dts cpu description Wesley W. Terpstra 2017-03-01 16:47:10 -08:00
  • cfd367248f rocketchip: add blind ports to DTS Wesley W. Terpstra 2017-03-01 00:03:01 -08:00
  • 9a5e2e038b uncore: add DTS meta-data for devices Wesley W. Terpstra 2017-02-28 23:12:36 -08:00
  • 0b950b5938 coreplex: bind assigned resources Wesley W. Terpstra 2017-02-28 22:34:24 -08:00
  • 7f6a250dbf tilelink2: add hooks for Resources Wesley W. Terpstra 2017-02-28 19:49:39 -08:00
  • e322692d16 diplomacy: add DeviceTree renderer Wesley W. Terpstra 2017-02-28 19:48:24 -08:00
  • c01a74f4a0 diplomacy: add AddressRange conversion to/from AddressSet Wesley W. Terpstra 2017-02-28 17:50:54 -08:00
  • bb70b1a3c3 diplomacy: add resource tracking Wesley W. Terpstra 2017-02-28 14:41:49 -08:00
  • 3a55a1afae Merge pull request #562 from ucb-bar/periphery-adjustments Henry Cook 2017-03-02 11:14:07 -08:00
  • 9544b8007e bump chisel3 Henry Cook 2017-03-02 10:41:26 -08:00
  • 9ce6898d46 firrtl: bump firrtl Henry Cook 2017-03-01 16:58:29 -08:00
  • 42cc61a80c Merge branch 'master' into periphery-adjustments Henry Cook 2017-03-01 16:38:51 -08:00
  • 859416de73 Show how to build riscv-tools in parallel (#530) edwardcwang 2017-03-01 15:54:34 -08:00
  • 9bfcb40cb4 util: Majority on sets of bools Henry Cook 2017-02-27 20:18:28 -08:00
  • 6958f05a85 Merge remote-tracking branch 'origin/master' into periphery-adjustments Henry Cook 2017-02-27 19:40:55 -08:00
  • d1bb82a1f8 Bump chisel3 and firrtl (#566) Jack Koenig 2017-02-27 19:38:23 -08:00
  • 62f5727bc6 periphery: peripheryBusBytes and socBusBytes Henry Cook 2017-02-27 19:19:41 -08:00
  • dfa61bc487 Standardize Data.holdUnless and SeqMem.readAndHold Andrew Waterman 2017-02-25 02:54:42 -08:00
  • fd972f5c67 icache: back-pressure is unnecessary (#564) Wesley W. Terpstra 2017-02-24 21:01:56 -08:00
  • 35877e6ec1 Merge branch 'master' into periphery-adjustments Henry Cook 2017-02-24 10:37:41 -08:00
  • 87d909e996 Fix HastiTestSRAM can't R/W byte when HSIZE is 0 (#563) Leway Colin 2017-02-25 02:37:26 +08:00
  • a281ad8ad2 rocketchip: rename some periphery ports Henry Cook 2017-02-23 14:25:17 -08:00
  • 6c3011d513 periphery: make external interrupts a UInt rather than a Vec[Bool] Henry Cook 2017-02-23 11:48:49 -08:00
  • c01aec9259 tilelink2: support unused IntXing Wesley W. Terpstra 2017-02-22 18:41:06 -08:00
  • 735e4f8ed6 diplomacy: use HeterogeneousBag instead of Vec Wesley W. Terpstra 2017-02-22 17:05:22 -08:00
  • 027d6247b6 diplomacy: silence a warning (#560) Henry Cook 2017-02-22 11:28:04 -08:00
  • 45d016a76f Bump chisel3 and firrtl (#557) Jack Koenig 2017-02-17 20:52:18 -08:00
  • 6ea35125d4 Merge pull request #556 from ucb-bar/rational-config Wesley W. Terpstra 2017-02-17 20:31:56 +01:00
  • 9153a9a733 ClockDivider: add docs to appease the reviewer Wesley W. Terpstra 2017-02-17 19:34:44 +01:00
  • 3931b0faff coreplex: assume L1 runs no slower than L2 Wesley W. Terpstra 2017-02-17 15:15:41 +01:00
  • 5045696f92 TLRational: test all corners Wesley W. Terpstra 2017-02-17 14:16:45 +01:00
  • 91d1880dbf ClockDivider2: fix launch alignment of clocks (vcs) Wesley W. Terpstra 2017-02-17 11:49:35 +01:00
  • 924afebbd9 tilelink2: make TLRational have configurable direction Wesley W. Terpstra 2017-02-17 04:19:00 +01:00
  • bb334a2cf5 util: add fast2slow direction option to rational crossings Wesley W. Terpstra 2017-02-17 03:55:46 +01:00
  • e51609aec0 build: support waveform debug using opensource tools Wesley W. Terpstra 2017-02-17 03:35:46 +01:00
  • abe344a1a4 tilelink2 Fuzzer: support read-only mode (#555) Wesley W. Terpstra 2017-02-13 00:18:47 +01:00