build: remove the now obsolete config string
This commit is contained in:
Wesley W. Terpstra
parent
93ca555c20
commit
d3c5318714
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@ -24,11 +24,6 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork {
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plic.intnode := intBar.intnode
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lazy val configString = {
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val managers = l1tol2.node.edgesIn(0).manager.managers
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rocketchip.GenerateConfigString(p, clint, plic, managers)
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}
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lazy val dts = DTS(bindingTree)
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}
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@ -52,9 +47,6 @@ trait CoreplexRISCVPlatformModule extends CoreplexNetworkModule {
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val rtcLast = Reg(init = Bool(false), next=rtcSync)
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outer.clint.module.io.rtcTick := Reg(init = Bool(false), next=(rtcSync & (~rtcLast)))
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println(s"\nGenerated Configuration String\n${outer.configString}")
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ElaborationArtefacts.add("cfg", outer.configString)
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println(outer.dts)
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ElaborationArtefacts.add("dts", outer.dts)
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}
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@ -305,7 +305,7 @@ trait PeripheryBootROM {
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private val bootrom_address = 0x1000
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private val bootrom_size = 0x1000
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private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.configString)
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private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.dts)
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val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
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bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
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}
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@ -52,50 +52,18 @@ class GlobalVariable[T] {
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def get: T = { require(assigned); variable }
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}
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object GenerateConfigString {
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def apply(p: Parameters, clint: CoreplexLocalInterrupter, plic: TLPLIC, peripheryManagers: Seq[TLManagerParameters]) = {
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val c = CoreplexParameters()(p)
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val res = new StringBuilder
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res append plic.globalConfigString
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res append clint.globalConfigString
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res append "core {\n"
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c.tilesParams.zipWithIndex.map { case(t, i) =>
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val isa = {
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val m = if (t.core.mulDiv.nonEmpty) "m" else ""
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val a = if (t.core.useAtomics) "a" else ""
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val f = if (t.core.fpu.nonEmpty) "f" else ""
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val d = if (t.core.fpu.nonEmpty && p(XLen) > 32) "d" else ""
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val c = if (t.core.useCompressed) "c" else ""
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val s = if (t.core.useVM) "s" else ""
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s"rv${p(XLen)}i$m$a$f$d$c$s"
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}
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res append s" $i {\n"
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res append " 0 {\n"
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res append s" isa $isa;\n"
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res append clint.hartConfigStrings(i)
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res append plic.hartConfigStrings(i)
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res append " };\n"
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res append " };\n"
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}
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res append "};\n"
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peripheryManagers.foreach { manager => res append manager.dts }
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res append '\u0000'
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res.toString
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}
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}
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object GenerateBootROM {
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def apply(p: Parameters, address: BigInt, configString: String) = {
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def apply(p: Parameters, address: BigInt, dts: String) = {
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val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
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val rom = ByteBuffer.wrap(romdata)
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rom.order(ByteOrder.LITTLE_ENDIAN)
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require(address == address.toInt)
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val configStringAddr = address.toInt + rom.capacity
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val dtsAddr = address.toInt + rom.capacity
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require(rom.getInt(12) == 0,
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"Config string address position should not be occupied by code")
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rom.putInt(12, configStringAddr)
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rom.array() ++ (configString.getBytes.toSeq)
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"DTS address position should not be occupied by code")
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rom.putInt(12, dtsAddr)
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rom.array() ++ (dts.getBytes.toSeq)
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}
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}
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@ -89,38 +89,6 @@ class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC00000
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def nPriorities = min(maxPriorities, nDevices)
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def nHarts = intnode.edgesOut.map(_.source.num).sum
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def context(i: Int, mode: Char) = mode match {
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case 'M' => i * contextsPerHart
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case 'S' => require(supervisor); i * contextsPerHart + 1
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}
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def claimAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode)) + PLICConsts.claimOffset
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def threshAddr(i: Int, mode: Char) = address + PLICConsts.hartBase(context(i, mode))
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def enableAddr(i: Int, mode: Char) = address + PLICConsts.enableBase(context(i, mode))
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// Create the global PLIC config string
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lazy val globalConfigString = Seq(
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s"plic {\n",
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s" priority 0x${address.toString(16)};\n",
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s" pending 0x${(address + PLICConsts.pendingBase).toString(16)};\n",
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s" ndevs ${nDevices};\n",
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s"};\n").mkString
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// Create the per-Hart config string
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lazy val hartConfigStrings = Seq.tabulate(intnode.edgesOut.size) { i => (Seq(
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s" plic {\n",
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s" m {\n",
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s" ie 0x${enableAddr(i, 'M').toString(16)};\n",
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s" thresh 0x${threshAddr(i, 'M').toString(16)};\n",
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s" claim 0x${claimAddr(i, 'M').toString(16)};\n",
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s" };\n") ++ (if (!supervisor) Seq() else Seq(
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s" s {\n",
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s" ie 0x${enableAddr(i, 'S').toString(16)};\n",
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s" thresh 0x${threshAddr(i, 'S').toString(16)};\n",
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s" claim 0x${claimAddr(i, 'S').toString(16)};\n",
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s" };\n")) ++ Seq(
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s" };\n")).mkString
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}
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// Assign all the devices unique ranges
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lazy val sources = intnode.edgesIn.map(_.source)
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lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
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@ -146,11 +114,12 @@ class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC00000
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// This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
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val harts = io.harts.flatten
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println("\nInterrupt map:")
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println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):")
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flatSources.foreach { s =>
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// +1 because 0 is reserved, +1-1 because the range is half-open
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println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}")
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}
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println("")
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require (nDevices == interrupts.size)
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require (nHarts == harts.size)
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@ -50,16 +50,6 @@ class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Paramet
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sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(ints, Seq(Resource(device, "int"))))) },
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sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) })
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// Legacy stuff:
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val globalConfigString = Seq(
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s"rtc {\n",
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s" addr 0x${(address + timeOffset).toString(16)};\n",
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s"};\n").mkString
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val hartConfigStrings = (0 until p(NTiles)).map { i => Seq(
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s" timecmp 0x${(address + timecmpOffset(i)).toString(16)};\n",
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s" ipi 0x${(address + msipOffset(i)).toString(16)};\n").mkString
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}
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val rtcTick = Bool(INPUT)
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@ -23,8 +23,7 @@ case class TLManagerParameters(
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supportsPutPartial: TransferSizes = TransferSizes.none,
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supportsHint: TransferSizes = TransferSizes.none,
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// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
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fifoId: Option[Int] = None,
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customDTS: Option[String]= None)
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fifoId: Option[Int] = None)
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{
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require (!address.isEmpty)
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address.foreach { a => require (a.finite) }
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@ -54,17 +53,6 @@ case class TLManagerParameters(
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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// Generate the config string (in future device tree)
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lazy val dts = customDTS.getOrElse {
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val header = s"${name} {\n"
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val middle = address.map { a =>
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require (a.contiguous) // Config String is not so flexible
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" addr 0x%x;\n size 0x%x;\n".format(a.base, a.mask+1)
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}
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val footer = "}\n"
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header + middle.reduce(_ + _) + footer
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}
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// The device had better not support a transfer larger than it's alignment
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val minAlignment = address.map(_.alignment).min
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require (minAlignment >= maxTransfer)
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