riscv/rocket-chip
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rocketchip: add blind ports to DTS

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This commit is contained in:
Wesley W. Terpstra 2017-03-01 00:03:01 -08:00
parent 9a5e2e038b
commit cfd367248f
8 changed files with 21 additions and 1 deletions
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15
src/main/scala/rocketchip/Periphery.scala
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@ -51,8 +51,14 @@ trait HasPeripheryParameters {
trait PeripheryExtInterrupts {
this: HasTopLevelNetworks =>
private val device = new Device with DeviceInterrupts {
def describe(resources: ResourceBindings): Description = {
Description("soc/offchip-interrupts", describeInterrupts(resources))
}
}
val nExtInterrupts = p(NExtTopInterrupts)
val extInterrupts = IntInternalInputNode(nExtInterrupts)
val extInterrupts = IntInternalInputNode(nExtInterrupts, device.int)
val extInterruptXing = LazyModule(new IntXing)
intBus.intnode := extInterruptXing.intnode
@ -84,6 +90,8 @@ trait PeripheryMasterAXI4Mem {
private val channels = p(BankedL2Config).nMemoryChannels
private val lineBytes = p(CacheBlockBytes)
private val device = new MemoryDevice
val mem_axi4 = AXI4BlindOutputNode(Seq.tabulate(channels) { channel =>
val base = AddressSet(config.base, config.size-1)
val filter = AddressSet(channel * lineBytes, ~((channels-1) * lineBytes))
@ -91,6 +99,7 @@ trait PeripheryMasterAXI4Mem {
AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = base.intersect(filter).toList,
resources = device.reg,
regionType = RegionType.UNCACHED, // cacheable
executable = true,
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
@ -160,9 +169,11 @@ trait PeripheryMasterAXI4MMIO {
this: HasTopLevelNetworks =>
private val config = p(ExtBus)
private val device = new SimpleDevice("mmio", Nil)
val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(BigInt(config.base), config.size-1)),
resources = device.reg,
executable = true, // Can we run programs on this memory?
supportsWrite = TransferSizes(1, 256), // The slave supports 1-256 byte transfers
supportsRead = TransferSizes(1, 256),
@ -227,9 +238,11 @@ trait PeripheryMasterTLMMIO {
this: HasTopLevelNetworks =>
private val config = p(ExtBus)
private val device = new SimpleDevice("mmio", Nil)
val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
managers = Seq(TLManagerParameters(
address = List(AddressSet(BigInt(config.base), config.size-1)),
resources = device.reg,
executable = true,
supportsGet = TransferSizes(1, cacheBlockBytes),
supportsPutFull = TransferSizes(1, cacheBlockBytes),

1
src/main/scala/uncore/ahb/Parameters.scala
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@ -9,6 +9,7 @@ import scala.math.max
case class AHBSlaveParameters(
address: Seq[AddressSet],
resources: Seq[Resource] = Nil,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false, // processor can execute from this memory
nodePath: Seq[BaseNode] = Seq(),

1
src/main/scala/uncore/apb/Parameters.scala
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@ -9,6 +9,7 @@ import scala.math.max
case class APBSlaveParameters(
address: Seq[AddressSet],
resources: Seq[Resource] = Nil,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false, // processor can execute from this memory
nodePath: Seq[BaseNode] = Seq(),

1
src/main/scala/uncore/axi4/Parameters.scala
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@ -9,6 +9,7 @@ import scala.math.max
case class AXI4SlaveParameters(
address: Seq[AddressSet],
resources: Seq[Resource] = Nil,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false, // processor can execute from this memory
nodePath: Seq[BaseNode] = Seq(),

1
src/main/scala/uncore/axi4/ToTL.scala
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@ -20,6 +20,7 @@ case class AXI4ToTLNode() extends MixedAdapterNode(AXI4Imp, TLImp)(
slaves = mp.managers.map { m =>
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,

1
src/main/scala/uncore/tilelink2/ToAHB.scala
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@ -19,6 +19,7 @@ case class TLToAHBNode() extends MixedAdapterNode(TLImp, AHBImp)(
val managers = slaves.map { case s =>
TLManagerParameters(
address = s.address,
resources = s.resources,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,

1
src/main/scala/uncore/tilelink2/ToAPB.scala
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@ -19,6 +19,7 @@ case class TLToAPBNode() extends MixedAdapterNode(TLImp, APBImp)(
val managers = slaves.map { case s =>
TLManagerParameters(
address = s.address,
resources = s.resources,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,

1
src/main/scala/uncore/tilelink2/ToAXI4.scala
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@ -23,6 +23,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedAdapterNode(TLImp, AXI4Imp)(
managers = p.slaves.map { case s =>
TLManagerParameters(
address = s.address,
resources = s.resources,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,