riscv/rocket-chip
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  • 0493372027 jtag_vpi: Attempt to more aggressively flush the simulator output as it is needed by other listeners Megan Wachs 2017-05-26 11:48:45 -07:00
  • 618468a06b Make plusarg_reader default args work with VCS (#765) Andrew Waterman 2017-05-24 21:38:56 -07:00
  • dbc5e7c494 Add TLB miss performance counters (#762) Andrew Waterman 2017-05-23 12:52:25 -07:00
  • b2b4c1abcd Separate tag ECC and data ECC options (#761) Andrew Waterman 2017-05-23 12:51:48 -07:00
  • 940614625e TLCacheCork: unsafe flag now _really_ unsafe (#760) Henry Cook 2017-05-22 19:37:11 -07:00
  • 7f1d3c445f Plusargs -- tilelink timeout detection from the command line (#752) Wesley W. Terpstra 2017-05-18 22:49:59 -07:00
  • 20704b1454 Merge pull request #753 from freechipsproject/debug_tests Wesley W. Terpstra 2017-05-18 22:20:21 -07:00
  • 24a533e77c debug: Bump riscv-tools to pick up correction in gdbserver Megan Wachs 2017-05-18 13:10:22 -07:00
  • 304e82486f Debug: Update makefile now that OpenOCD is part of riscv-tools Megan Wachs 2017-05-18 12:26:34 -07:00
  • 26194b3078 bump riscv-tools to pick up latest version of debug tests Megan Wachs 2017-05-18 12:00:16 -07:00
  • ada5439c3e dont use env to force caches to be the same (#754) Colin Schmidt 2017-05-18 18:46:29 -07:00
  • 55e8d28868 Merge pull request #747 from freechipsproject/try-travis-stages Wesley W. Terpstra 2017-05-18 14:14:54 -07:00
  • d0c00eccb9 caches don't transfer across sudo flag changes Colin Schmidt 2017-05-18 11:33:23 -07:00
  • 617dd6fe1e try travis suggestion on the jvm stages Colin Schmidt 2017-05-18 11:06:43 -07:00
  • 08eb7b0410 Bump firrtl for bug fixes in annotation propagation and DCE (#751) Jack Koenig 2017-05-18 10:54:30 -07:00
  • 991a67ac68 Merge pull request #749 from freechipsproject/unit-test-speedup Henry Cook 2017-05-17 16:28:42 -07:00
  • 733ebbce0e Update README.md (#748) Henry Cook 2017-05-17 14:53:56 -07:00
  • 66d660ff60 use YAML to condense script replication Colin Schmidt 2017-05-17 14:41:04 -07:00
  • 748a48f667 unittest: balance the run times of the tests Wesley W. Terpstra 2017-05-17 14:02:14 -07:00
  • bea2489507 unittest: make overall test duration configurable Wesley W. Terpstra 2017-05-17 12:17:08 -07:00
  • c8ba6b2feb unittests: accept a configurable number of transactions to run Wesley W. Terpstra 2017-05-17 11:56:01 -07:00
  • f6f40b1442 unit tests: all should accept timeout override Wesley W. Terpstra 2017-05-17 11:37:23 -07:00
  • 4acc302158 unittest: disable XBar test from regression (covered by other tests) Wesley W. Terpstra 2017-05-17 11:26:11 -07:00
  • 0c382204d4 give them all stages Colin Schmidt 2017-05-17 12:38:52 -07:00
  • 62a54e6bdb inline the env matrix Colin Schmidt 2017-05-17 12:36:49 -07:00
  • 2f3e22aff6 matrix outside after jobs Colin Schmidt 2017-05-17 12:34:11 -07:00
  • f3775cbbbf try moving matrix into jobs Colin Schmidt 2017-05-17 12:31:13 -07:00
  • dfabf68d9c Merge pull request #746 from freechipsproject/fix-bundle-refs Henry Cook 2017-05-17 12:28:46 -07:00
  • b7dc415522 maybe this will order them with deploy last Colin Schmidt 2017-05-17 12:28:01 -07:00
  • b9fc169367 try another stages organization Colin Schmidt 2017-05-17 12:24:41 -07:00
  • 83a5230e91 change install to script? Colin Schmidt 2017-05-17 12:13:31 -07:00
  • bce613ce38 try using a new travis staging feature Colin Schmidt 2017-05-17 11:58:09 -07:00
  • 8c3736e0dc tilelink2: remove ready-valid fuzzer obsoleted by TLDelayer Wesley W. Terpstra 2017-05-17 06:47:21 -07:00
  • 1f2236cdb3 diplomacy: appease Jack by removing unused 1st bundles argument Wesley W. Terpstra 2017-05-17 06:46:07 -07:00
  • f2d16d49c2 tilelink2: don't widen TLMonitor interface unnecessarily Wesley W. Terpstra 2017-05-16 21:01:58 -07:00
  • 191dad7800 diplomacy: provide connect access to edges without bundles Wesley W. Terpstra 2017-05-16 20:51:55 -07:00
  • 65053978dc Merge pull request #745 from freechipsproject/tile-xbar Wesley W. Terpstra 2017-05-17 06:28:37 -07:00
  • d8996ea85f Empty commit to force travis Megan Wachs 2017-05-16 22:56:58 -07:00
  • 5f22e91a7f rocc: fix RoccExampleConfig Henry Cook 2017-05-16 16:44:53 -07:00
  • a19fc2549e tile: add tileBus xbar Henry Cook 2017-05-16 16:12:01 -07:00
  • ad087dd18d Merge pull request #742 from ucb-bar/true-rational Wesley W. Terpstra 2017-05-15 15:51:35 -07:00
  • 3e2b477c0a rational: adjust comments and add a case for N:M Wesley W. Terpstra 2017-05-14 15:11:29 -07:00
  • 2119df5a60 vsrc: add ClockDivider3 used to simulate unaligned clocks Wesley W. Terpstra 2017-05-14 13:29:36 -07:00
  • 05e7501e7a build: include chiselName and give an example of using it (#738) Wesley W. Terpstra 2017-05-12 06:25:58 -07:00
  • 18725a05b0 DTS tweaks (#740) Wesley W. Terpstra 2017-05-12 05:32:57 -07:00
  • a69fcd50dd Bump Firrtl to add new global DCE (#741) Jack Koenig 2017-05-12 00:36:49 -07:00
  • 23706113c2 Bump riscv-tools, to get some -mcmodel=medany fixes (#739) Palmer Dabbelt 2017-05-11 21:04:33 -07:00
  • 5f3a4ada1b diplomacy: add legalize method to AddressSet Henry Cook 2017-05-09 11:12:17 -07:00
  • 3af40bff8b tilelink: better address masking for fuzzing Henry Cook 2017-05-08 18:48:40 -07:00
  • 9720a53eae Merge pull request #735 from ucb-bar/early-ack-frag-fix Wesley W. Terpstra 2017-05-09 18:22:59 -07:00
  • 3eaa973da7 tilelink2: add earlyAck to regression Wesley W. Terpstra 2017-05-09 16:34:29 -07:00
  • 3e7bdcbf5e tilelink2: Fragmenter should ignore error when not valid Wesley W. Terpstra 2017-05-09 16:37:36 -07:00
  • 43c9f5fe7e tilelink2: keep earlyAck Fragmenter sources distinct Wesley W. Terpstra 2017-05-09 16:29:21 -07:00
  • 19db0389b6 Merge pull request #732 from ucb-bar/vectored-stvec Palmer Dabbelt 2017-05-09 09:34:47 -07:00
  • 3a9bbd7e58 Merge branch 'master' into vectored-stvec Andrew Waterman 2017-05-08 14:08:09 -07:00
  • fd76f45f65 Merge pull request #731 from ucb-bar/axi-zero-width Wesley W. Terpstra 2017-05-08 10:48:32 -07:00
  • 2d8a49cc06 tilelink2: Fragmenter client must request global FIFO Wesley W. Terpstra 2017-05-08 00:56:45 -07:00
  • 36f4584bb1 axi4: Test AXI4-Lite in regression Wesley W. Terpstra 2017-05-08 00:31:35 -07:00
  • 3209e58845 axi4: SRAM support 0 userBits Wesley W. Terpstra 2017-05-08 00:30:40 -07:00
  • db76ff2d86 axi4: Deinterleaver must gather R also for single ID Wesley W. Terpstra 2017-05-08 00:07:45 -07:00
  • 8fc27b0bf2 axi4: IdIndexer; a single ID does NOT imply no response interleaving Wesley W. Terpstra 2017-05-08 00:03:07 -07:00
  • 4847c32599 tilelink: ToAXI4 - must interlock till last beat Wesley W. Terpstra 2017-05-08 00:00:40 -07:00
  • 8169ba6411 axi4: IdIndexer now handles 0-width IDs Wesley W. Terpstra 2017-05-07 13:10:51 -07:00
  • 7eefc12705 Support vectored stvec interrupts, too Andrew Waterman 2017-05-07 15:14:51 -07:00
  • c6135a02df Revert "rocket: hard-wire UXL/SXL fields to 0" Andrew Waterman 2017-05-05 15:17:35 -07:00
  • dd1546fd69 Check PPN LSBs for superpage PTEs Andrew Waterman 2017-05-05 14:42:14 -07:00
  • 431e726c29 Merge pull request #727 from ucb-bar/fix-axi2tl-timeout Yunsup Lee 2017-05-04 01:42:48 -07:00
  • 1b3b228790 ITIM supports PutPartial Scott Johnson 2017-05-03 19:29:47 -07:00
  • 398600d4da Interlock to prevent ITIM hazard when tl.a.valid & tl.d.valid & !tl.d.ready Andrew Waterman 2017-05-04 00:24:13 -07:00
  • 1cc665717d Wes fix for AXI2TL timeout when writes backed up Scott Johnson 2017-05-04 00:07:08 -07:00
  • e21b74c232 Merge pull request #724 from ucb-bar/rvc-speculative Andrew Waterman 2017-05-03 18:48:49 -07:00
  • fa6ecdf813 Fix RVC/uncacheable instruction memory performance bug Andrew Waterman 2017-05-03 17:52:06 -07:00
  • 7b3d87a2e6 Merge pull request #723 from ucb-bar/fuzz-ranges Henry Cook 2017-05-03 16:30:10 -07:00
  • 1f1240baf1 fuzzer: allow fuzzing range to be overridden Henry Cook 2017-05-03 15:29:14 -07:00
  • cd547fabbd Merge pull request #695 from ucb-bar/pipeline-mmio Henry Cook 2017-05-03 11:25:24 -07:00
  • f8c92d2669 Merge branch 'master' into pipeline-mmio Megan Wachs 2017-05-03 08:37:12 -07:00
  • 4efcb5a139 Increase frontend decoupling (#722) Andrew Waterman 2017-05-03 07:54:46 -07:00
  • 05ca88fb47 Merge branch 'master' into pipeline-mmio Henry Cook 2017-05-03 01:59:59 -07:00
  • 922a8ef5e0 local_interrupts: Correct off-by-1 if there is no SEIP Megan Wachs 2017-05-02 19:24:19 -07:00
  • 4dd3345db2 Merge branch 'master' into pipeline-mmio Henry Cook 2017-05-02 16:23:26 -07:00
  • 1ecd63611f Merge pull request #718 from ucb-bar/dtim-putpartial Yunsup Lee 2017-05-02 15:42:28 -07:00
  • 3a1a37d41b Support PutPartial in ScratchpadSlavePort Andrew Waterman 2017-05-02 03:04:41 -07:00
  • 938b089543 Remove legacy devices that use AMOALU Andrew Waterman 2017-05-02 01:59:47 -07:00
  • f8151ce786 Remove subword load muxing in ScratchpadSlavePort Andrew Waterman 2017-05-01 17:36:39 -07:00
  • 044b6ed3f9 Improve logical ops in AMOALU Andrew Waterman 2017-04-30 02:22:19 -07:00
  • f49172b5bc ScratchpadSlavePort doesn't support byte/halfword atomics Andrew Waterman 2017-04-29 16:47:49 -07:00
  • fe280187a1 axi4: Fragmenter cuts all input channel readys Wesley W. Terpstra 2017-05-01 22:52:33 -07:00
  • 3d06f01a2c rocket: turn on early ack for ITIM Wesley W. Terpstra 2017-04-28 08:41:31 -07:00
  • 58a4529cc5 axi4: the last missing piece for safe FIFO ordering Wesley W. Terpstra 2017-04-27 17:55:51 -07:00
  • b0b5601e8d axi4: ToTL correct error handling Wesley W. Terpstra 2017-04-27 16:21:01 -07:00
  • 661015a78d axi4: switch arbiter to round robin Wesley W. Terpstra 2017-04-27 14:40:49 -07:00
  • 976af7a8c7 tilelink2: better width inference for {left,right}OR Wesley W. Terpstra 2017-04-27 13:21:25 -07:00
  • 40f18e6e43 diplomacy: optimize IdRange overlap detection Wesley W. Terpstra 2017-04-26 20:49:18 -07:00
  • 30f1f1e7c7 rocket: turn on early ack for DTIM Wesley W. Terpstra 2017-04-26 17:42:04 -07:00
  • 6ee69454c3 tilelink2: Fragmenter now supports early Ack Wesley W. Terpstra 2017-04-26 17:39:57 -07:00
  • e09fa866b7 tilelink2: FIFOFixer should NOT change client request status Wesley W. Terpstra 2017-04-26 16:48:35 -07:00
  • b040a462c9 Wes's change to remove user bits from external AXI interface, and add 1 cycle latency to make sure external AXI is compliant Scott Johnson 2017-04-26 16:46:57 -07:00
  • a71f708dc7 rocketchip: move the Error device to 0x3000 Wesley W. Terpstra 2017-04-26 13:18:55 -07:00
  • d27e1928dd axi4: make maxFlight a per-master parameter Wesley W. Terpstra 2017-04-25 18:49:33 -07:00
  • e1a072a644 axi4: massage test cases into shape again Wesley W. Terpstra 2017-04-25 17:56:06 -07:00