Merge pull request #727 from ucb-bar/fix-axi2tl-timeout
Wes's fix for AXI2TL timeout when writes backed up
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431e726c29
@ -47,6 +47,7 @@ class ICache(val latency: Int, val hartid: Int)(implicit p: Parameters) extends
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsPutFull = TransferSizes(1, wordBytes),
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supportsPutPartial = TransferSizes(1, wordBytes),
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supportsGet = TransferSizes(1, wordBytes),
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fifoId = Some(0))), // requests handled in FIFO order
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beatBytes = wordBytes,
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@ -226,7 +227,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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io.resp.valid := s2_valid && s2_hit && !s2_disparity
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tl_in.map { tl =>
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tl.a.ready := !(tl_out.d.valid || s1_slaveValid || s2_slaveValid || s3_slaveValid)
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val respValid = RegInit(false.B)
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tl.a.ready := !(tl_out.d.valid || s1_slaveValid || s2_slaveValid || s3_slaveValid || respValid)
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val s1_a = RegEnable(tl.a.bits, s0_slaveValid)
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when (s0_slaveValid) {
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val a = tl.a.bits
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@ -243,7 +245,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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}
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assert(!s2_valid || RegNext(RegNext(s0_vaddr)) === io.s2_vaddr)
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when (!(tl.a.valid || s1_slaveValid || s2_slaveValid)
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when (!(tl.a.valid || s1_slaveValid || s2_slaveValid || respValid)
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&& s2_valid && s2_data_decoded.correctable && !s2_tag_disparity) {
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// handle correctable errors on CPU accesses to the scratchpad.
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// if there is an in-flight slave-port access to the scratchpad,
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@ -254,7 +256,6 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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s1s3_slaveAddr := Cat(OHToUInt(s2_tag_hit), io.s2_vaddr(untagBits-1, log2Ceil(wordBits/8)), s1s3_slaveAddr(log2Ceil(wordBits/8)-1, 0))
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}
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val respValid = RegInit(false.B)
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respValid := s2_slaveValid || (respValid && !tl.d.ready)
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when (s2_slaveValid) {
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when (edge_in.get.hasData(s1_a) || s2_data_decoded.correctable) { s3_slaveValid := true }
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@ -50,9 +50,11 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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val numIds = edgeIn.master.endId
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val beatBytes = edgeOut.manager.beatBytes
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val countBits = AXI4Parameters.lenBits + (1 << AXI4Parameters.sizeBits) - 1
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val beatCountBits = AXI4Parameters.lenBits + (1 << AXI4Parameters.sizeBits) - 1
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val maxFlight = edgeIn.master.masters.map(_.maxFlight.get).max
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val addedBits = log2Ceil(maxFlight) + 1
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val logFlight = log2Ceil(maxFlight)
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val txnCountBits = log2Ceil(maxFlight+1) // wrap-around must not block b_allow
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val addedBits = logFlight + 1 // +1 for read vs. write source ID
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require (edgeIn.master.userBits == 0, "AXI4 user bits cannot be transported by TL")
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require (edgeIn.master.masters(0).aligned)
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@ -72,10 +74,10 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
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val r_size = OH1ToUInt(r_size1)
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val r_ok = edgeOut.manager.supportsGetSafe(in.ar.bits.addr, r_size)
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val r_addr = Mux(r_ok, in.ar.bits.addr, UInt(error) | in.ar.bits.addr(log2Up(beatBytes)-1, 0))
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val r_count = RegInit(Vec.fill(numIds) { UInt(0, width = log2Ceil(maxFlight)) })
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val r_id = Cat(in.ar.bits.id, r_count(in.ar.bits.id), UInt(0, width=1))
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val r_count = RegInit(Vec.fill(numIds) { UInt(0, width = txnCountBits) })
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val r_id = Cat(in.ar.bits.id, r_count(in.ar.bits.id)(logFlight-1,0), UInt(0, width=1))
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assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, countBits)) // because aligned
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assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, beatCountBits)) // because aligned
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in.ar.ready := r_out.ready
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r_out.valid := in.ar.valid
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r_out.bits := edgeOut.Get(r_id, r_addr, r_size)._2
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@ -90,10 +92,10 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
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val w_size = OH1ToUInt(w_size1)
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val w_ok = edgeOut.manager.supportsPutPartialSafe(in.aw.bits.addr, w_size)
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val w_addr = Mux(w_ok, in.aw.bits.addr, UInt(error) | in.aw.bits.addr(log2Up(beatBytes)-1, 0))
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val w_count = RegInit(Vec.fill(numIds) { UInt(0, width = log2Ceil(maxFlight)) })
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val w_id = Cat(in.aw.bits.id, w_count(in.aw.bits.id), UInt(1, width=1))
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val w_count = RegInit(Vec.fill(numIds) { UInt(0, width = txnCountBits) })
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val w_id = Cat(in.aw.bits.id, w_count(in.aw.bits.id)(logFlight-1,0), UInt(1, width=1))
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assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, countBits)) // because aligned
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assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, beatCountBits)) // because aligned
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assert (!in.aw.valid || in.aw.bits.len === UInt(0) || in.aw.bits.size === UInt(log2Ceil(beatBytes))) // because aligned
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in.aw.ready := w_out.ready && in.w.valid && in.w.bits.last
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in.w.ready := w_out.ready && in.aw.valid
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@ -134,7 +136,7 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
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// We need to prevent sending B valid before the last W beat is accepted
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// TileLink allows early acknowledgement of a write burst, but AXI does not.
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val b_count = RegInit(Vec.fill(numIds) { UInt(0, width = log2Ceil(maxFlight)) })
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val b_count = RegInit(Vec.fill(numIds) { UInt(0, width = txnCountBits) })
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val b_allow = b_count(in.b.bits.id) =/= w_count(in.b.bits.id)
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val b_sel = UIntToOH(in.b.bits.id, numIds)
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