Merge pull request #723 from ucb-bar/fuzz-ranges
Allow TL fuzzing range to be overridden
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commit
7b3d87a2e6
@ -62,10 +62,14 @@ class AXI4FullFuzzRAMTest(implicit p: Parameters) extends UnitTest(500000) {
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io.finished := dut.io.finished
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}
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class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
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trait HasFuzzTarget {
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val fuzzAddr = AddressSet(0x0, 0xfff)
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}
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class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule with HasFuzzTarget
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{
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val node = AXI4OutputNode()
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val fuzz = LazyModule(new TLFuzzer(5000))
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val fuzz = LazyModule(new TLFuzzer(5000, overrideAddress = Some(fuzzAddr)))
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val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
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model.node := fuzz.node
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@ -88,11 +92,11 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
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}
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}
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class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
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class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTarget
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{
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val node = AXI4InputNode()
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val xbar = LazyModule(new TLXbar)
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val ram = LazyModule(new TLRAM(AddressSet(0x0, 0xfff)))
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val ram = LazyModule(new TLRAM(fuzzAddr))
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val error= LazyModule(new TLError(Seq(AddressSet(0x1800, 0xff))))
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ram.node := TLFragmenter(4, 16)(xbar.node)
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@ -82,7 +82,8 @@ class TLFuzzer(
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(wide: Int, increment: Bool, abs_values: Int) =>
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LFSRNoiseMaker(wide=wide, increment=increment)
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},
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noModify: Boolean = false)(implicit p: Parameters) extends LazyModule
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noModify: Boolean = false,
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overrideAddress: Option[AddressSet] = None)(implicit p: Parameters) extends LazyModule
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{
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val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,inFlight)))
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@ -96,7 +97,7 @@ class TLFuzzer(
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val edge = node.edgesOut(0)
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// Extract useful parameters from the TL edge
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val endAddress = edge.manager.maxAddress + 1
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val endAddress = overrideAddress.map(_.max).getOrElse(edge.manager.maxAddress)
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val maxTransfer = edge.manager.maxTransfer
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val beatBytes = edge.manager.beatBytes
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val maxLgBeats = log2Up(maxTransfer/beatBytes)
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