riscv/rocket-chip
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101 Commits

Author SHA1 Message Date
Andrew Waterman
c7110c8389 Make FPU pipeline depths configurable 2014-02-28 13:39:59 -08:00
Andrew Waterman
95de358a96 More of the same FPU fix 
some SP ops followed by DP stores were not working because they
were encoded as subnormals, not NaNs.
 2014-01-17 14:09:30 -08:00
Andrew Waterman
cf38001e98 Fix fmv.s.x -> fsd 2014-01-17 03:52:35 -08:00
Andrew Waterman
924261e2b2 Update to new privileged ISA... phew 2013-11-25 04:35:15 -08:00
Andrew Waterman
1d2f4f8437 New ISA encoding, AUIPC semantics 2013-09-21 06:32:40 -07:00
Andrew Waterman
18968dfbc7 Move store data generation into cache 2013-09-14 16:15:07 -07:00
Andrew Waterman
d4a0db4575 Reflect ISA changes 2013-08-24 14:43:55 -07:00
Henry Cook
3a266cbbfa final Reg changes 2013-08-15 15:28:15 -07:00
Henry Cook
b570435847 Reg standardization 2013-08-13 17:50:02 -07:00
Henry Cook
d9b3c7cfc8 Moved RenEn to ChiselUtil 2013-08-12 22:18:25 -07:00
Henry Cook
1a9e43aa11 initial attempt at upgrade 2013-08-12 10:39:11 -07:00
Henry Cook
9abdf4e154 Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object. 2013-07-23 20:27:58 -07:00
Yunsup Lee
60bd3a6413 Revert "shuffled FPU control logic around to make functional unit retiming work better" 
This reverts commit 20dd308067b143adff4913fc7ac710a393ca1d86.
 2013-01-29 19:34:55 -08:00
Rimas Avizienis
f2df6147df shuffled FPU control logic around to make functional unit retiming work better 2013-01-28 17:17:09 -08:00
Henry Cook
e1225c5114 standardize IO naming convention 2013-01-07 13:41:36 -08:00
Andrew Waterman
4608660f6e torture revealed a couple bugs 
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
 2012-12-04 05:57:53 -08:00
Andrew Waterman
cc067026a2 pipeline D$ response -> FPU regfile 2012-11-17 06:48:11 -08:00
Andrew Waterman
8dce89703a new D$ with better QoR and AMO pipelining 
Vector unit is disabled because nack handling needs to be fixed.
 2012-11-16 02:39:33 -08:00
Andrew Waterman
4d1ca8ba3a remove more global consts; refactor DTLBs 
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
 2012-11-06 08:13:44 -08:00
Andrew Waterman
7380c9fe60 aggressively clock gate int and fp datapaths 2012-11-04 16:40:14 -08:00
Huy Vo
fd95159837 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Andrew Waterman
f645fb4dd7 add L2$ 
It still has performance bugs but no correctness bugs AFAIK.
 2012-07-10 05:23:29 -07:00
Andrew Waterman
5035374f36 update to new chisel 2012-07-08 17:59:41 -07:00
Andrew Waterman
4e5f874266 update to new chisel/hwacha 2012-06-08 00:13:14 -07:00
Andrew Waterman
7f6319047e update to new scala/chisel/Mem 2012-06-06 02:47:22 -07:00
Huy Vo
7408c9ab69 removing wires 2012-05-24 10:42:39 -07:00
Andrew Waterman
65ff397122 improved instruction decoding 
it now makes use of don't-cares by performing logic minimization
 2012-05-01 20:16:36 -07:00
Andrew Waterman
5819beed64 use parameterized FP units 2012-05-01 01:25:43 -07:00
Andrew Waterman
7f254d9670 refine FP bugfixes 2012-04-01 14:52:33 -07:00
Huy Vo
c7c35322c2 two bug fixes to fpu 2012-03-31 22:23:51 -07:00
Andrew Waterman
7eb73c325e fix signedness of zero fmul results 
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0.  Now we
add -0.0 if rs1*rs2 is negative.
 2012-03-10 00:21:51 -08:00
Yunsup Lee
8678b3d70c clean up ioDecoupled/ioPipe interface 2012-03-01 20:48:46 -08:00
Yunsup Lee
20d0088f66 temporary fix to match bit widths for Mem 2012-02-29 17:09:31 -08:00
Yunsup Lee
94ba32bbd3 change package name and sbt project name to rocket 2012-02-25 17:09:26 -08:00
Andrew Waterman
5332bab6f1 expose FMA ports outside of FPU (for the VU) 2012-02-23 17:39:34 -08:00
Andrew Waterman
0ec7767c13 declaring success on FPU for now 2012-02-14 19:11:57 -08:00
Andrew Waterman
38c67e5a9e add fmin.[s|d] and fmax.[s|d] 2012-02-14 06:37:18 -08:00
Andrew Waterman
ee9fc10668 add fcvt.s.d, fcvt.d.s 2012-02-14 06:03:43 -08:00
Andrew Waterman
ce202c73d1 add fsgnj[n|x].[s|d] 2012-02-14 04:24:35 -08:00
Andrew Waterman
15dc2d8c40 add fp writeback arbitration logic 2012-02-14 00:32:25 -08:00
Andrew Waterman
6c2d8a37ae remove a partial update that makes chisel barf 
chisel regards it as a combinational loop, even though it isn't.
 2012-02-13 16:45:29 -08:00
Andrew Waterman
b5a19a54a3 add fcvt.[s|d].[w|l][u] 2012-02-13 02:01:26 -08:00
Andrew Waterman
a4a9d2312c add fcvt.[w|l][u].[s|d], f[eq|lt|le].[s|d] 2012-02-13 01:30:01 -08:00
Andrew Waterman
069037ff3a add FP recoding 2012-02-12 23:31:50 -08:00
Andrew Waterman
08b6517a23 add FP ops mftx, mxtf, mtfsr, mffsr 2012-02-12 20:12:53 -08:00
Andrew Waterman
9bb1558a34 WIP on FPU 2012-02-12 04:36:01 -08:00
Andrew Waterman
50a283d311 move store data generation into EX stage 
doing so removes it from the critical path of FP store unrecoding.
 2012-02-12 01:35:55 -08:00
Andrew Waterman
725190d0ee update to new chisel 2012-02-11 17:20:33 -08:00
Andrew Waterman
990e3a1b34 fix fpu port direction bug 2012-02-08 15:19:26 -08:00
Andrew Waterman
d471a8b2da arbitrate for LLFU writebacks in MEM stage 2012-02-08 04:21:05 -08:00
Andrew Waterman
5403d069e9 add fp loads/stores 2012-02-07 23:54:25 -08:00