359 lines
11 KiB
Scala
359 lines
11 KiB
Scala
package Top
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import Chisel._
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import Node._
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import Constants._
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import Instructions._
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object rocketFPConstants
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{
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val FCMD_ADD = Bits("b000000")
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val FCMD_SUB = Bits("b000001")
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val FCMD_MUL = Bits("b000010")
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val FCMD_DIV = Bits("b000011")
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val FCMD_SQRT = Bits("b000100")
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val FCMD_SGNINJ = Bits("b000101")
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val FCMD_SGNINJN = Bits("b000110")
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val FCMD_SGNMUL = Bits("b000111")
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val FCMD_CVT_L_FMT = Bits("b001000")
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val FCMD_CVT_LU_FMT = Bits("b001001")
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val FCMD_CVT_W_FMT = Bits("b001010")
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val FCMD_CVT_WU_FMT = Bits("b001011")
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val FCMD_CVT_FMT_L = Bits("b001100")
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val FCMD_CVT_FMT_LU = Bits("b001101")
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val FCMD_CVT_FMT_W = Bits("b001110")
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val FCMD_CVT_FMT_WU = Bits("b001111")
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val FCMD_CVT_FMT_S = Bits("b010000")
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val FCMD_CVT_FMT_D = Bits("b010001")
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val FCMD_EQ = Bits("b010101")
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val FCMD_LT = Bits("b010110")
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val FCMD_LE = Bits("b010111")
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val FCMD_MIN = Bits("b011000")
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val FCMD_MAX = Bits("b011001")
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val FCMD_MFTX = Bits("b011100")
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val FCMD_MFFSR = Bits("b011101")
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val FCMD_MXTF = Bits("b011110")
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val FCMD_MTFSR = Bits("b011111")
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val FCMD_MADD = Bits("b100100")
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val FCMD_MSUB = Bits("b100101")
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val FCMD_NMSUB = Bits("b100110")
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val FCMD_NMADD = Bits("b100111")
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val FCMD_LOAD = Bits("b111000")
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val FCMD_STORE = Bits("b111001")
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val FCMD_WIDTH = 6
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val FSR_WIDTH = 8
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}
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import rocketFPConstants._
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class rocketFPUCtrlSigs extends Bundle
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{
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val cmd = Bits(width = FCMD_WIDTH)
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val valid = Bool()
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val wen = Bool()
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val ren1 = Bool()
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val ren2 = Bool()
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val ren3 = Bool()
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val single = Bool()
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val fromint = Bool()
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val toint = Bool()
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val store = Bool()
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val fsr = Bool()
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}
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class rocketFPUDecoder extends Component
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{
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val io = new Bundle {
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val inst = Bits(32, INPUT)
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val sigs = new rocketFPUCtrlSigs().asOutput
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}
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// val fp =
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// ListLookup(io.dpath.inst,
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// List(FPU_N, FPU_N, FPU_N, FPU_N, FPU_N),
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// Array(
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// FMOVZ -> List(Bool(true)),
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// FMOVN -> List(Bool(true)),
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// FADD_S -> List(Bool(true)),
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// FSUB_S -> List(Bool(true)),
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// FMUL_S -> List(Bool(true)),
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// FDIV_S -> List(Bool(true)),
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// FSQRT_S -> List(Bool(true)),
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// FSGNJ_S -> List(Bool(true)),
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// FSGNJN_S -> List(Bool(true)),
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// FSGNJX_S -> List(Bool(true)),
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// FADD_D -> List(Bool(true)),
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// FSUB_D -> List(Bool(true)),
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// FMUL_D -> List(Bool(true)),
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// FDIV_D -> List(Bool(true)),
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// FSQRT_D -> List(Bool(true)),
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// FSGNJ_D -> List(Bool(true)),
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// FSGNJN_D -> List(Bool(true)),
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// FSGNJX_D -> List(Bool(true)),
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// FCVT_L_S -> List(Bool(true)),
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// FCVT_LU_S -> List(Bool(true)),
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// FCVT_W_S -> List(Bool(true)),
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// FCVT_WU_S -> List(Bool(true)),
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// FCVT_L_D -> List(Bool(true)),
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// FCVT_LU_D -> List(Bool(true)),
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// FCVT_W_D -> List(Bool(true)),
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// FCVT_WU_D -> List(Bool(true)),
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// FCVT_S_L -> List(Bool(true)),
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// FCVT_S_LU -> List(Bool(true)),
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// FCVT_S_W -> List(Bool(true)),
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// FCVT_S_WU -> List(Bool(true)),
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// FCVT_D_L -> List(Bool(true)),
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// FCVT_D_LU -> List(Bool(true)),
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// FCVT_D_W -> List(Bool(true)),
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// FCVT_D_WU -> List(Bool(true)),
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// FCVT_S_D -> List(Bool(true)),
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// FCVT_D_S -> List(Bool(true)),
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// FEQ_S -> List(Bool(true)),
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// FLT_S -> List(Bool(true)),
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// FLE_S -> List(Bool(true)),
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// FEQ_D -> List(Bool(true)),
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// FLT_D -> List(Bool(true)),
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// FLE_D -> List(Bool(true)),
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// FMIN_S -> List(Bool(true)),
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// FMAX_S -> List(Bool(true)),
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// FMIN_D -> List(Bool(true)),
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// FMAX_D -> List(Bool(true)),
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// MFTX_S -> List(Bool(true)),
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// MFTX_D -> List(Bool(true)),
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// MFFSR -> List(Bool(true)),
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// MXTF_S -> List(Bool(true)),
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// MXTF_D -> List(Bool(true)),
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// MTFSR -> List(Bool(true)),
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// FLW -> List(FPU_Y, FPU_Y, FPU_N, FPU_N, FPU_N),
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// FLD -> List(FPU_Y, FPU_Y, FPU_N, FPU_N, FPU_N),
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// FSW -> List(FPU_Y, FPU_N, FPU_N, FPU_Y, FPU_N),
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// FSD -> List(FPU_Y, FPU_N, FPU_N, FPU_Y, FPU_N)
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// FMADD_S -> List(Bool(true)),
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// FMSUB_S -> List(Bool(true)),
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// FNMSUB_S -> List(Bool(true)),
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// FNMADD_S -> List(Bool(true)),
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// FMADD_D -> List(Bool(true)),
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// FMSUB_D -> List(Bool(true)),
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// FNMSUB_D -> List(Bool(true)),
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// FNMADD_D -> List(Bool(true))
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// ));
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val N = Bool(false)
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val Y = Bool(true)
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val X = Bool(false)
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val FCMD_X = FCMD_ADD
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val decoder = ListLookup(io.inst,
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List (N,FCMD_X, X,X,X,X,X,X,X,X,X),
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Array(FLW -> List(Y,FCMD_LOAD, Y,N,N,N,Y,N,N,N,N),
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FLD -> List(Y,FCMD_LOAD, Y,N,N,N,N,N,N,N,N),
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FSW -> List(Y,FCMD_STORE, N,N,Y,N,Y,N,N,Y,N),
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FSD -> List(Y,FCMD_STORE, N,N,Y,N,N,N,N,Y,N),
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MXTF_S -> List(Y,FCMD_MXTF, Y,N,N,N,Y,Y,N,N,N),
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MXTF_D -> List(Y,FCMD_MXTF, Y,N,N,N,N,Y,N,N,N),
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MFTX_S -> List(Y,FCMD_MFTX, N,Y,N,N,Y,N,Y,N,N),
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MFTX_D -> List(Y,FCMD_MFTX, N,Y,N,N,N,N,Y,N,N),
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MTFSR -> List(Y,FCMD_MTFSR, N,N,N,N,Y,Y,Y,N,Y),
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MFFSR -> List(Y,FCMD_MFFSR, N,N,N,N,Y,N,Y,N,Y)
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))
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val valid :: cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: store :: fsr :: Nil = decoder
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io.sigs.valid := valid.toBool
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io.sigs.cmd := cmd
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io.sigs.wen := wen.toBool
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io.sigs.ren1 := ren1.toBool
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io.sigs.ren2 := ren2.toBool
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io.sigs.ren3 := ren3.toBool
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io.sigs.single := single.toBool
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io.sigs.fromint := fromint.toBool
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io.sigs.toint := toint.toBool
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io.sigs.store := store.toBool
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io.sigs.fsr := fsr.toBool
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}
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class ioDpathFPU extends Bundle {
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val inst = Bits(32, OUTPUT)
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val fromint_data = Bits(64, OUTPUT)
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val store_data = Bits(64, INPUT)
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val toint_data = Bits(64, INPUT)
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val dmem_resp_val = Bool(OUTPUT)
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val dmem_resp_tag = UFix(5, OUTPUT)
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val dmem_resp_data = Bits(64, OUTPUT)
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}
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class ioCtrlFPU extends Bundle {
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val valid = Bool(OUTPUT)
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val nack = Bool(INPUT)
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val killx = Bool(OUTPUT)
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val killm = Bool(OUTPUT)
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val dec = new rocketFPUCtrlSigs().asInput
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}
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class rocketFPIntUnit extends Component
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{
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val io = new Bundle {
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val single = Bool(INPUT)
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val cmd = Bits(FCMD_WIDTH, INPUT)
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val fsr = Bits(FSR_WIDTH, INPUT)
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val in = Bits(65, INPUT)
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val store_data = Bits(64, OUTPUT)
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val toint_data = Bits(64, OUTPUT)
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val exc = Bits(5, OUTPUT)
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}
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val unrecoded_s = io.in(31,0)
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val unrecoded_d = io.in
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io.store_data := Mux(io.single, Cat(unrecoded_s, unrecoded_s), unrecoded_d)
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val scmp = Bool(false)
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val scmp_exc = Bits(0)
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val s2i = UFix(0)
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val s2i_exc = Bits(0)
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val dcmp = Bool(false)
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val dcmp_exc = Bits(0)
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val d2i = UFix(0)
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val d2i_exc = Bits(0)
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// output muxing
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val (out_s, exc_s) = (Wire() { Bits() }, Wire() { Bits() })
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out_s := Cat(Fill(32, unrecoded_s(31)), unrecoded_s)
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exc_s := Bits(0)
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val (out_d, exc_d) = (Wire() { Bits() }, Wire() { Bits() })
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out_d := unrecoded_d
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exc_d := Bits(0)
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when (io.cmd === FCMD_MTFSR || io.cmd === FCMD_MFFSR) {
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out_s := io.fsr
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}
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when (io.cmd === FCMD_CVT_W_FMT || io.cmd === FCMD_CVT_WU_FMT) {
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out_s := Cat(Fill(32, s2i(31)), s2i(31,0))
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exc_s := s2i_exc
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out_d := Cat(Fill(32, d2i(31)), d2i(31,0))
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exc_d := d2i_exc
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}
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when (io.cmd === FCMD_CVT_L_FMT || io.cmd === FCMD_CVT_LU_FMT) {
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out_s := s2i
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exc_s := s2i_exc
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out_d := d2i
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exc_d := d2i_exc
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}
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when (io.cmd === FCMD_EQ || io.cmd === FCMD_LT || io.cmd === FCMD_LE) {
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out_s := scmp
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exc_s := scmp_exc
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out_d := dcmp
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exc_d := dcmp_exc
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}
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io.toint_data := Mux(io.single, out_s, out_d)
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io.exc := Mux(io.single, exc_s, exc_d)
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}
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class rocketFPU extends Component
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{
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val io = new Bundle {
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val ctrl = new ioCtrlFPU().flip()
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val dpath = new ioDpathFPU().flip()
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}
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val reg_inst = Reg() { Bits() }
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when (io.ctrl.valid) {
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reg_inst := io.dpath.inst
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}
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val reg_valid = Reg(io.ctrl.valid, Bool(false))
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val fp_decoder = new rocketFPUDecoder
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fp_decoder.io.inst := io.dpath.inst
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val ctrl = Reg() { new rocketFPUCtrlSigs }
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when (io.ctrl.valid) {
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ctrl := fp_decoder.io.sigs
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}
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// load response
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val load_wb = Reg(io.dpath.dmem_resp_val, resetVal = Bool(false))
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val load_wb_data = Reg() { Bits(width = 64) } // XXX WTF why doesn't bit width inference work for the regfile?!
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val load_wb_tag = Reg() { UFix() }
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when (io.dpath.dmem_resp_val) {
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load_wb_data := io.dpath.dmem_resp_data
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load_wb_tag := io.dpath.dmem_resp_tag
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}
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val fsr_rm = Reg() { Bits(width = 3) }
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val fsr_exc = Reg() { Bits(width = 5) }
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// regfile
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val regfile = Mem(32, load_wb, load_wb_tag, load_wb_data);
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regfile.setReadLatency(0);
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regfile.setTarget('inst);
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val ex_rs1 = regfile.read(reg_inst(26,22))
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val ex_rs2 = regfile.read(reg_inst(21,17))
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val ex_rs3 = regfile.read(reg_inst(16,12))
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val fp_fromint_val = Reg(resetVal = Bool(false))
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val fp_fromint_data = Reg() { Bits() }
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val fp_toint_val = Reg(resetVal = Bool(false))
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val fp_toint_data = Reg() { Bits() }
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val fp_toint_single = Reg() { Bool() }
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val fp_toint_cmd = Reg() { Bits() }
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val fp_waddr = Reg() { Bits() }
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fp_fromint_val := Bool(false)
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fp_toint_val := Bool(false)
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when (reg_valid && !io.ctrl.killx) {
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fp_waddr := reg_inst(31,27)
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when (ctrl.fromint) {
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fp_fromint_val := Bool(true)
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fp_fromint_data := io.dpath.fromint_data
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}
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when (ctrl.toint) {
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fp_toint_val := Bool(true)
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fp_toint_data := ex_rs1
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}
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when (ctrl.store) {
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fp_toint_data := ex_rs2
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}
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when (ctrl.toint || ctrl.store) {
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fp_toint_single := ctrl.single
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fp_toint_cmd := ctrl.cmd
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}
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}
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// currently we assume FP stores and FP->int ops take 1 cycle (MEM)
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val fpiu = new rocketFPIntUnit
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fpiu.io.single := ctrl.single
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fpiu.io.cmd := ctrl.cmd
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fpiu.io.fsr := Cat(fsr_rm, fsr_exc)
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fpiu.io.in := fp_toint_data
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io.dpath.store_data := fpiu.io.store_data
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io.dpath.toint_data := fpiu.io.toint_data
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val retire_toint = Reg(!io.ctrl.killm && fp_toint_val, resetVal = Bool(false))
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val retire_toint_exc = Reg(fpiu.io.exc)
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val retire_fromint = Reg(!io.ctrl.killm && fp_fromint_val, resetVal = Bool(false))
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val retire_fromint_wdata = Reg(fp_fromint_data)
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val retire_fromint_waddr = Reg(fp_waddr)
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when (retire_toint) {
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fsr_exc := fsr_exc | retire_toint_exc
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}
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when (retire_toint && retire_fromint) { // MTFSR
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fsr_exc := retire_fromint_wdata(4,0)
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fsr_rm := retire_fromint_wdata(7,5)
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}
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regfile.write(retire_fromint_waddr, retire_fromint_wdata, retire_fromint && !retire_toint)
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val fp_inflight = fp_toint_val || retire_toint || fp_fromint_val || retire_fromint
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val mtfsr_inflight = fp_toint_val && fp_fromint_val || retire_toint && retire_fromint
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val fsr_busy = ctrl.fsr && fp_inflight || mtfsr_inflight
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val units_busy = Bool(false)
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val write_port_busy = Bool(false)
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io.ctrl.nack := fsr_busy || units_busy || write_port_busy
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io.ctrl.dec <> fp_decoder.io.sigs
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}
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