149 lines
4.5 KiB
Scala
149 lines
4.5 KiB
Scala
package Top
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import Chisel._
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import Node._;
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import Constants._
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import Instructions._
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class rocketFPUDecoder extends Component
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{
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val io = new Bundle {
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val inst = Bits(32, INPUT)
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val valid = Bool(OUTPUT)
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val wen = Bool(OUTPUT)
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val ren1 = Bool(OUTPUT)
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val ren2 = Bool(OUTPUT)
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val ren3 = Bool(OUTPUT)
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}
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// val fp =
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// ListLookup(io.dpath.inst,
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// List(FPU_N, FPU_N, FPU_N, FPU_N, FPU_N),
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// Array(
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// FMOVZ -> List(Bool(true)),
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// FMOVN -> List(Bool(true)),
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// FADD_S -> List(Bool(true)),
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// FSUB_S -> List(Bool(true)),
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// FMUL_S -> List(Bool(true)),
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// FDIV_S -> List(Bool(true)),
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// FSQRT_S -> List(Bool(true)),
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// FSGNJ_S -> List(Bool(true)),
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// FSGNJN_S -> List(Bool(true)),
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// FSGNJX_S -> List(Bool(true)),
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// FADD_D -> List(Bool(true)),
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// FSUB_D -> List(Bool(true)),
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// FMUL_D -> List(Bool(true)),
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// FDIV_D -> List(Bool(true)),
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// FSQRT_D -> List(Bool(true)),
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// FSGNJ_D -> List(Bool(true)),
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// FSGNJN_D -> List(Bool(true)),
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// FSGNJX_D -> List(Bool(true)),
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// FCVT_L_S -> List(Bool(true)),
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// FCVT_LU_S -> List(Bool(true)),
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// FCVT_W_S -> List(Bool(true)),
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// FCVT_WU_S -> List(Bool(true)),
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// FCVT_L_D -> List(Bool(true)),
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// FCVT_LU_D -> List(Bool(true)),
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// FCVT_W_D -> List(Bool(true)),
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// FCVT_WU_D -> List(Bool(true)),
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// FCVT_S_L -> List(Bool(true)),
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// FCVT_S_LU -> List(Bool(true)),
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// FCVT_S_W -> List(Bool(true)),
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// FCVT_S_WU -> List(Bool(true)),
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// FCVT_D_L -> List(Bool(true)),
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// FCVT_D_LU -> List(Bool(true)),
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// FCVT_D_W -> List(Bool(true)),
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// FCVT_D_WU -> List(Bool(true)),
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// FCVT_S_D -> List(Bool(true)),
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// FCVT_D_S -> List(Bool(true)),
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// FEQ_S -> List(Bool(true)),
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// FLT_S -> List(Bool(true)),
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// FLE_S -> List(Bool(true)),
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// FEQ_D -> List(Bool(true)),
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// FLT_D -> List(Bool(true)),
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// FLE_D -> List(Bool(true)),
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// FMIN_S -> List(Bool(true)),
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// FMAX_S -> List(Bool(true)),
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// FMIN_D -> List(Bool(true)),
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// FMAX_D -> List(Bool(true)),
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// MFTX_S -> List(Bool(true)),
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// MFTX_D -> List(Bool(true)),
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// MFFSR -> List(Bool(true)),
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// MXTF_S -> List(Bool(true)),
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// MXTF_D -> List(Bool(true)),
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// MTFSR -> List(Bool(true)),
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// FLW -> List(FPU_Y, FPU_Y, FPU_N, FPU_N, FPU_N),
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// FLD -> List(FPU_Y, FPU_Y, FPU_N, FPU_N, FPU_N),
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// FSW -> List(FPU_Y, FPU_N, FPU_N, FPU_Y, FPU_N),
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// FSD -> List(FPU_Y, FPU_N, FPU_N, FPU_Y, FPU_N)
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// FMADD_S -> List(Bool(true)),
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// FMSUB_S -> List(Bool(true)),
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// FNMSUB_S -> List(Bool(true)),
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// FNMADD_S -> List(Bool(true)),
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// FMADD_D -> List(Bool(true)),
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// FMSUB_D -> List(Bool(true)),
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// FNMSUB_D -> List(Bool(true)),
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// FNMADD_D -> List(Bool(true))
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// ));
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val N = Bool(false)
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val Y = Bool(true)
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val decoder = ListLookup(io.inst,
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List (N, N, N, N, N),
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Array(FLW -> List(Y, Y, N, N, N),
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FLD -> List(Y, Y, N, N, N),
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FSW -> List(Y, N, N, Y, N),
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FSD -> List(Y, N, N, Y, N)))
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val valid :: wen :: ren1 :: ren2 :: ren3 :: Nil = decoder
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io.valid := valid.toBool
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io.wen := wen.toBool
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io.ren1 := ren1.toBool
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io.ren2 := ren2.toBool
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io.ren3 := ren3.toBool
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}
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class ioDpathFPU extends Bundle {
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val store_data = Bits(64, INPUT)
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}
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class rocketFPU extends Component
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{
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val io = new Bundle {
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val req_valid = Bool(INPUT)
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val req_ready = Bool(OUTPUT)
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val req_cmd = Bits(6, INPUT)
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val req_inst = Bits(32, INPUT)
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val killx = Bool(INPUT)
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val killm = Bool(INPUT)
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val dmem = new ioDmem(List("resp_val", "resp_tag", "resp_data"))
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val dpath = new ioDpathFPU().flip()
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}
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val ex_reg_inst = Reg() { Bits() }
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when (io.req_valid) {
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ex_reg_inst <== io.req_inst
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}
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// load response
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val dmem_resp_val_fpu = io.dmem.resp_val && io.dmem.resp_tag(0).toBool
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val load_wb = Reg(dmem_resp_val_fpu, resetVal = Bool(false))
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val load_wb_data = Reg() { Bits() }
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val load_wb_tag = Reg() { UFix() }
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when (dmem_resp_val_fpu) {
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load_wb_data <== io.dmem.resp_data
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load_wb_tag <== io.dmem.resp_tag.toUFix >> UFix(1)
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}
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// regfile
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val regfile = Mem4(32, load_wb_data);
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regfile.setReadLatency(0);
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regfile.setTarget('inst);
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regfile.write(load_wb_tag, load_wb_data, load_wb);
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io.req_ready := Bool(true)
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io.dpath.store_data := regfile(ex_reg_inst(21,17))
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}
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