Andrew Waterman
121e4fb511
Flip direction of some bulk connects
2015-08-03 18:01:14 -07:00
Andrew Waterman
9c7a41e8d3
Chisel3: bulk connect is not commutative
...
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:09:00 -07:00
Henry Cook
c70b495f6d
moved buses to junctions repo
2015-07-29 18:04:30 -07:00
Andrew Waterman
3c0475e08b
Add Wire() wrap
2015-07-15 20:24:03 -07:00
Andrew Waterman
2d6b3b2331
Don't use clone
2015-07-15 18:06:27 -07:00
Henry Cook
f3a838cedf
nasti converters, hub bugfix
2015-05-21 19:49:17 -07:00
Henry Cook
a7fa77c7fc
track operand size for Gets
2015-05-13 23:28:18 -07:00
Henry Cook
90ced93eeb
Merge branch 'master' into gh-pages
2015-05-07 12:35:14 -07:00
Henry Cook
1e05fc0525
First pages commit
2015-04-29 13:18:26 -07:00
Henry Cook
4c7969b2b3
Metadata docs and api cleanup
2015-04-20 16:32:09 -07:00
Henry Cook
6d40a61060
TileLink scala doc and parameter renaming
2015-04-19 22:06:44 -07:00
Henry Cook
ba7a8b1752
TileLink refactor; TileLinkPorts now available. L2Banks no longer have unique ids (suitable for hierarhical P&R).
2015-04-17 16:55:20 -07:00
Henry Cook
ce3271aef2
refactor LNClients and LNManagers
2015-04-15 15:48:36 -07:00
Henry Cook
90f800d87d
Grant bugfixes and more comments
2015-04-13 15:57:06 -07:00
Henry Cook
9708d25dff
Restructure L2 state machine and utilize HeaderlessTileLinkIO
2015-04-06 12:19:51 -07:00
Henry Cook
8959b2e81a
TileLinkEnqueuer
2015-03-26 13:29:52 -07:00
Henry Cook
5c2461c743
merge data wmask bugfix
2015-03-17 13:09:47 -07:00
Henry Cook
23f8033df5
turn off self probes again
2015-03-17 13:09:46 -07:00
Henry Cook
3f070eee1f
first cut of merging puts/gets
2015-03-17 13:09:44 -07:00
Henry Cook
f6d1a2fb76
No more self-probes required
2015-03-16 00:09:38 -07:00
Yunsup Lee
3a78ca210d
bugfix in uncached TL to TL convertors
2015-03-12 16:33:41 -07:00
Henry Cook
dcc84c4dd3
arbiter probe ready bugfix
2015-03-12 16:02:51 -07:00
Albert Ou
8f8022379c
Fix AMO opcode extraction
2015-03-11 23:24:58 -07:00
Albert Ou
f75126c39c
Require self probes for all built-in Acquire types
...
This ensures that puts by the RoCC accelerator properly invalidates its
tile's L1 D$, with which it currently shares the same TileLink port.
2015-03-11 23:24:58 -07:00
Henry Cook
1aff919c24
added prefetchAck Grant type
2015-03-11 17:32:06 -07:00
Henry Cook
b4ed1d9121
Add builtin prefetch types to TileLink
2015-03-11 14:28:17 -07:00
Henry Cook
a1f04386f7
Headerless TileLinkIO and arbiters
2015-03-09 16:34:59 -07:00
Henry Cook
1bed6ea498
New metadata-based coherence API
2015-02-28 17:32:03 -08:00
Henry Cook
0c66e70f14
cleanup of conflicts; allocation bugfix
2015-02-06 13:20:44 -08:00
Henry Cook
6141b3efc5
uncached -> builtin_type
2015-02-02 01:02:06 -08:00
Henry Cook
3aa030f960
Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor.
2015-02-01 20:37:16 -08:00
Henry Cook
9ef00d187f
%s/master/manager/g + better comments
2014-12-29 22:55:58 -08:00
Henry Cook
6a8b66231c
Add uncached->cached tilelink converter
2014-12-12 17:06:03 -08:00
Henry Cook
424df2368f
1R/W L2 data array?
...
Add TLDataBeats to new LLC; all bmarks pass
2014-12-12 17:05:21 -08:00
Henry Cook
3026c46a9c
Finish adding TLDataBeats to uncore & hub
2014-12-12 17:04:52 -08:00
Henry Cook
2f733a60db
Begin adding TLDataBeats to uncore
2014-12-12 17:04:31 -08:00
Henry Cook
a519a43f23
Merge branch 'master' into new-llc
...
Conflicts:
src/main/scala/coherence.scala
src/main/scala/memserdes.scala
src/main/scala/tilelink.scala
2014-11-12 16:25:25 -08:00
Henry Cook
cb7e712599
Added uncached write data queue to coherence hub
2014-11-12 12:55:07 -08:00
Henry Cook
82155f333e
Major tilelink revision for uncached message types
2014-11-11 17:36:55 -08:00
Henry Cook
10309849b7
Remove master_xact_id from Probe and Release
2014-11-06 12:07:33 -08:00
Henry Cook
86bdbd6535
new tshrs, compiles but does not elaborate
2014-10-07 22:33:10 -07:00
Henry Cook
d735f64110
Parameter API update
2014-10-02 16:47:35 -07:00
Henry Cook
82fe22f958
support for multiple tilelink paramerterizations in same design
...
Conflicts:
src/main/scala/cache.scala
2014-09-24 11:30:40 -07:00
Yunsup Lee
0b51d70bd2
add LICENSE
2014-09-12 15:31:38 -07:00
Henry Cook
f411fdcce3
Full conversion to params. Compiles but does not elaborate.
2014-08-08 12:21:57 -07:00
Henry Cook
1163131d1e
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:17:05 -07:00
Henry Cook
3f53d532c2
uniquify tilelink conf val name for easier subtyping
2014-04-26 14:58:38 -07:00
Henry Cook
b1df49ba30
removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
2014-04-10 12:35:43 -07:00
Henry Cook
fbca7c6bb3
refactor ioMem and associcated constants. merge Aqcuire and AcquireData
2014-04-10 12:35:43 -07:00
Henry Cook
bbf8010230
cleanups supporting uncore hierarchy
2014-01-31 15:59:21 -08:00