931 lines
33 KiB
Scala
931 lines
33 KiB
Scala
// See LICENSE for license details.
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package uncore
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import Chisel._
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import scala.math.max
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import scala.reflect._
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import scala.reflect.runtime.universe._
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// Parameters exposed to the top-level design, set based on
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// external requirements or design space exploration
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//
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case object TLId extends Field[String] // Unique name per network
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case object TLCoherencePolicy extends Field[CoherencePolicy]
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case object TLBlockAddrBits extends Field[Int]
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case object TLMaxClientXacts extends Field[Int]
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case object TLMaxClientPorts extends Field[Int]
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case object TLMaxManagerXacts extends Field[Int]
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case object TLDataBits extends Field[Int]
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case object TLDataBeats extends Field[Int]
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case object TLNetworkIsOrderedP2P extends Field[Boolean]
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abstract trait TileLinkParameters extends UsesParameters {
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val tlBlockAddrBits = params(TLBlockAddrBits)
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val tlMaxClientXacts = params(TLMaxClientXacts)
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val tlMaxClientPorts = params(TLMaxClientPorts)
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val tlMaxManagerXacts = params(TLMaxManagerXacts)
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val tlClientXactIdBits = log2Up(tlMaxClientXacts*tlMaxClientPorts)
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val tlManagerXactIdBits = log2Up(tlMaxManagerXacts)
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val tlDataBits = params(TLDataBits)
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val tlDataBytes = tlDataBits/8
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val tlDataBeats = params(TLDataBeats)
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val tlCoh = params(TLCoherencePolicy)
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val tlWriteMaskBits = if(tlDataBits/8 < 1) 1 else tlDataBits/8
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val tlBeatAddrBits = log2Up(tlDataBeats)
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val tlByteAddrBits = log2Up(tlWriteMaskBits)
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val tlMemoryOpcodeBits = M_SZ
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val tlMemoryOperandSizeBits = MT_SZ
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val tlAcquireTypeBits = max(log2Up(Acquire.nBuiltInTypes),
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tlCoh.acquireTypeWidth)
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val tlAcquireUnionBits = max(tlWriteMaskBits,
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(tlByteAddrBits +
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tlMemoryOperandSizeBits +
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tlMemoryOpcodeBits)) + 1
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val tlGrantTypeBits = max(log2Up(Grant.nBuiltInTypes),
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tlCoh.grantTypeWidth) + 1
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val tlNetworkPreservesPointToPointOrdering = params(TLNetworkIsOrderedP2P)
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val amoAluOperandBits = params(AmoAluOperandBits)
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}
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abstract class TLBundle extends Bundle with TileLinkParameters {
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}
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abstract class TLModule extends Module with TileLinkParameters
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// Directionality of message channel
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// Used to hook up logical network ports to physical network ports
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trait TileLinkChannel extends TLBundle {
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def hasData(dummy: Int = 0): Bool
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def hasMultibeatData(dummy: Int = 0): Bool
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}
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trait ClientToManagerChannel extends TileLinkChannel
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trait ManagerToClientChannel extends TileLinkChannel
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trait ClientToClientChannel extends TileLinkChannel // Unused for now
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// Common signals that are used in multiple channels.
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// These traits are useful for type parameterization.
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//
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trait HasCacheBlockAddress extends TLBundle {
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val addr_block = UInt(width = tlBlockAddrBits)
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def conflicts(that: HasCacheBlockAddress) = this.addr_block === that.addr_block
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def conflicts(addr: UInt) = this.addr_block === addr
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}
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trait HasTileLinkBeatId extends TLBundle {
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val addr_beat = UInt(width = tlBeatAddrBits)
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}
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trait HasClientTransactionId extends TLBundle {
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val client_xact_id = Bits(width = tlClientXactIdBits)
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}
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trait HasManagerTransactionId extends TLBundle {
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val manager_xact_id = Bits(width = tlManagerXactIdBits)
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}
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trait HasTileLinkData extends HasTileLinkBeatId {
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val data = UInt(width = tlDataBits)
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def hasData(dummy: Int = 0): Bool
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def hasMultibeatData(dummy: Int = 0): Bool
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}
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// Actual TileLink channel bundle definitions
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class Acquire extends ClientToManagerChannel
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with HasCacheBlockAddress
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with HasClientTransactionId
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with HasTileLinkData {
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// Actual bundle fields
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val is_builtin_type = Bool()
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val a_type = UInt(width = tlAcquireTypeBits)
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val union = Bits(width = tlAcquireUnionBits)
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// Utility funcs for accessing subblock union
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val opCodeOff = 1
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val opSizeOff = tlMemoryOpcodeBits + opCodeOff
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val addrByteOff = tlMemoryOperandSizeBits + opSizeOff
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val addrByteMSB = tlByteAddrBits + addrByteOff
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def allocate(dummy: Int = 0) = union(0)
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def op_code(dummy: Int = 0) = Mux(isBuiltInType(Acquire.putType) || isBuiltInType(Acquire.putBlockType),
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M_XWR, union(opSizeOff-1, opCodeOff))
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def op_size(dummy: Int = 0) = union(addrByteOff-1, opSizeOff)
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def addr_byte(dummy: Int = 0) = union(addrByteMSB-1, addrByteOff)
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private def amo_offset(dummy: Int = 0) = addr_byte()(tlByteAddrBits-1, log2Up(amoAluOperandBits/8))
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def amo_shift_bits(dummy: Int = 0) = UInt(amoAluOperandBits)*amo_offset()
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def wmask(dummy: Int = 0) =
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Mux(isBuiltInType(Acquire.putAtomicType),
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FillInterleaved(amoAluOperandBits/8, UIntToOH(amo_offset())),
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Mux(isBuiltInType(Acquire.putBlockType) || isBuiltInType(Acquire.putType),
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union(tlWriteMaskBits, 1),
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UInt(0, width = tlWriteMaskBits)))
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def full_wmask(dummy: Int = 0) = FillInterleaved(8, wmask())
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def addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, this.addr_byte())
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// Other helper funcs
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def is(t: UInt) = a_type === t //TODO: make this more opaque; def ===?
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def isBuiltInType(dummy: Int = 0): Bool = is_builtin_type
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def isBuiltInType(t: UInt): Bool = is_builtin_type && a_type === t
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def isSubBlockType(dummy: Int = 0): Bool = isBuiltInType() && Acquire.typesOnSubBlocks.contains(a_type)
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def isPrefetch(dummy: Int = 0): Bool = isBuiltInType() && is(Acquire.prefetchType)
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// Assumes no custom types have data
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def hasData(dummy: Int = 0): Bool = isBuiltInType() && Acquire.typesWithData.contains(a_type)
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def hasMultibeatData(dummy: Int = 0): Bool = Bool(tlDataBeats > 1) && isBuiltInType() &&
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Acquire.typesWithMultibeatData.contains(a_type)
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def requiresSelfProbe(dummy: Int = 0) = Bool(false)
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def getBuiltInGrantType(dummy: Int = 0): UInt = {
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MuxLookup(this.a_type, Grant.putAckType, Array(
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Acquire.getType -> Grant.getDataBeatType,
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Acquire.getBlockType -> Grant.getDataBlockType,
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Acquire.putType -> Grant.putAckType,
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Acquire.putBlockType -> Grant.putAckType,
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Acquire.putAtomicType -> Grant.getDataBeatType,
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Acquire.prefetchType -> Grant.prefetchAckType))
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}
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}
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object Acquire {
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val nBuiltInTypes = 5
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//TODO: Use Enum
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def getType = UInt("b000")
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def getBlockType = UInt("b001")
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def putType = UInt("b010")
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def putBlockType = UInt("b011")
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def putAtomicType = UInt("b100")
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def prefetchType = UInt("b101")
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def typesWithData = Vec(putType, putBlockType, putAtomicType)
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def typesWithMultibeatData = Vec(putBlockType)
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def typesOnSubBlocks = Vec(putType, getType, putAtomicType)
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def fullWriteMask = SInt(-1, width = new Acquire().tlWriteMaskBits).toUInt
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// Most generic constructor
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def apply(
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is_builtin_type: Bool,
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a_type: Bits,
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0),
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union: UInt = UInt(0)): Acquire = {
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val acq = new Acquire
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acq.is_builtin_type := is_builtin_type
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acq.a_type := a_type
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acq.client_xact_id := client_xact_id
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acq.addr_block := addr_block
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acq.addr_beat := addr_beat
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acq.data := data
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acq.union := union
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acq
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}
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// Copy constructor
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def apply(a: Acquire): Acquire = {
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val acq = new Acquire
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acq := a
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acq
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}
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}
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// Asks for a single TileLink beat of data
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object Get {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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alloc: Bool = Bool(true)): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.getType,
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client_xact_id = client_xact_id,
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addr_block = addr_block,
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addr_beat = addr_beat,
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union = Cat(M_XRD, alloc))
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}
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}
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// Asks for an entire cache block of data
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object GetBlock {
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def apply(
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client_xact_id: UInt = UInt(0),
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addr_block: UInt,
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alloc: Bool = Bool(true)): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.getBlockType,
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client_xact_id = client_xact_id,
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addr_block = addr_block,
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union = Cat(M_XRD, alloc))
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}
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}
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// Prefetch a cache block into the next level of the memory hierarchy
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// with read permissions
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object GetPrefetch {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.prefetchType,
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client_xact_id = client_xact_id,
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addr_block = addr_block,
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addr_beat = UInt(0),
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union = Cat(M_XRD, Bool(true)))
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}
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}
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// Writes up to a single TileLink beat of data, using mask
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object Put {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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data: UInt,
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wmask: UInt = Acquire.fullWriteMask): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.putType,
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addr_block = addr_block,
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addr_beat = addr_beat,
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client_xact_id = client_xact_id,
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data = data,
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union = Cat(wmask, Bool(true)))
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}
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}
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// Writes an entire cache block of data
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object PutBlock {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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data: UInt,
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wmask: UInt): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.putBlockType,
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client_xact_id = client_xact_id,
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addr_block = addr_block,
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addr_beat = addr_beat,
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data = data,
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union = Cat(wmask, (wmask != Acquire.fullWriteMask)))
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}
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def apply(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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data: UInt,
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alloc: Bool = Bool(true)): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.putBlockType,
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client_xact_id = client_xact_id,
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addr_block = addr_block,
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addr_beat = addr_beat,
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data = data,
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union = Cat(Acquire.fullWriteMask, alloc))
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}
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}
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// Performs an atomic operation in the outer memory
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object PutAtomic {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt,
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addr_byte: UInt,
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atomic_opcode: UInt,
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operand_size: UInt,
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data: UInt): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.putAtomicType,
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client_xact_id = client_xact_id,
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addr_block = addr_block,
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addr_beat = addr_beat,
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data = data,
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union = Cat(addr_byte, operand_size, atomic_opcode, Bool(true)))
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}
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}
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// Prefetch a cache block into the next level of the memory hierarchy
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// with write permissions
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object PutPrefetch {
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def apply(
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client_xact_id: UInt,
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addr_block: UInt): Acquire = {
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Acquire(
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is_builtin_type = Bool(true),
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a_type = Acquire.prefetchType,
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client_xact_id = client_xact_id,
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addr_block = addr_block,
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addr_beat = UInt(0),
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union = Cat(M_XWR, Bool(true)))
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}
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}
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class Probe extends ManagerToClientChannel
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with HasCacheBlockAddress {
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val p_type = UInt(width = tlCoh.probeTypeWidth)
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def is(t: UInt) = p_type === t
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def hasData(dummy: Int = 0) = Bool(false)
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def hasMultibeatData(dummy: Int = 0) = Bool(false)
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}
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object Probe {
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def apply(p_type: UInt, addr_block: UInt) = {
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val prb = new Probe
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prb.p_type := p_type
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prb.addr_block := addr_block
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prb
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}
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}
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class Release extends ClientToManagerChannel
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with HasCacheBlockAddress
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with HasClientTransactionId
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with HasTileLinkData {
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val r_type = UInt(width = tlCoh.releaseTypeWidth)
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val voluntary = Bool()
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// Helper funcs
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def is(t: UInt) = r_type === t
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def hasData(dummy: Int = 0) = tlCoh.releaseTypesWithData.contains(r_type)
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//TODO: Assumes all releases write back full cache blocks:
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def hasMultibeatData(dummy: Int = 0) = Bool(tlDataBeats > 1) && tlCoh.releaseTypesWithData.contains(r_type)
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def isVoluntary(dummy: Int = 0) = voluntary
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def requiresAck(dummy: Int = 0) = !Bool(tlNetworkPreservesPointToPointOrdering)
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}
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object Release {
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def apply(
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voluntary: Bool,
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r_type: UInt,
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client_xact_id: UInt,
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addr_block: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): Release = {
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val rel = new Release
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rel.r_type := r_type
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rel.client_xact_id := client_xact_id
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rel.addr_block := addr_block
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rel.addr_beat := addr_beat
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rel.data := data
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rel.voluntary := voluntary
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rel
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}
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}
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class Grant extends ManagerToClientChannel
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with HasTileLinkData
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with HasClientTransactionId
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with HasManagerTransactionId {
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val is_builtin_type = Bool()
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val g_type = UInt(width = tlGrantTypeBits)
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// Helper funcs
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def isBuiltInType(dummy: Int = 0): Bool = is_builtin_type
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def isBuiltInType(t: UInt): Bool = is_builtin_type && g_type === t
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def is(t: UInt):Bool = g_type === t
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def hasData(dummy: Int = 0): Bool = Mux(isBuiltInType(),
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Grant.typesWithData.contains(g_type),
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tlCoh.grantTypesWithData.contains(g_type))
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def hasMultibeatData(dummy: Int = 0): Bool =
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Bool(tlDataBeats > 1) && Mux(isBuiltInType(),
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Grant.typesWithMultibeatData.contains(g_type),
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tlCoh.grantTypesWithData.contains(g_type))
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def isVoluntary(dummy: Int = 0): Bool = isBuiltInType() && (g_type === Grant.voluntaryAckType)
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def requiresAck(dummy: Int = 0): Bool = !Bool(tlNetworkPreservesPointToPointOrdering) && !isVoluntary()
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def makeFinish(dummy: Int = 0): Finish = {
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val f = Bundle(new Finish, { case TLMaxManagerXacts => tlMaxManagerXacts })
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f.manager_xact_id := this.manager_xact_id
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f
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}
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}
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object Grant {
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val nBuiltInTypes = 5
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def voluntaryAckType = UInt("b000")
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def putAckType = UInt("b001")
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def prefetchAckType = UInt("b011")
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def getDataBeatType = UInt("b100")
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def getDataBlockType = UInt("b101")
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def typesWithData = Vec(getDataBlockType, getDataBeatType)
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def typesWithMultibeatData= Vec(getDataBlockType)
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def apply(
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is_builtin_type: Bool,
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g_type: UInt,
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client_xact_id: UInt,
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manager_xact_id: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): Grant = {
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val gnt = new Grant
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gnt.is_builtin_type := is_builtin_type
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gnt.g_type := g_type
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gnt.client_xact_id := client_xact_id
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gnt.manager_xact_id := manager_xact_id
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gnt.addr_beat := addr_beat
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gnt.data := data
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gnt
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}
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}
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class Finish extends ClientToManagerChannel with HasManagerTransactionId {
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def hasData(dummy: Int = 0) = Bool(false)
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def hasMultibeatData(dummy: Int = 0) = Bool(false)
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}
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// Complete IO definitions for two types of TileLink clients
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class UncachedTileLinkIO extends TLBundle {
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val acquire = new DecoupledIO(new LogicalNetworkIO(new Acquire))
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val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip
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val finish = new DecoupledIO(new LogicalNetworkIO(new Finish))
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}
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class TileLinkIO extends UncachedTileLinkIO {
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val probe = new DecoupledIO(new LogicalNetworkIO(new Probe)).flip
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val release = new DecoupledIO(new LogicalNetworkIO(new Release))
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}
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// Converts UncachedTileLinkIO to regular TileLinkIO by pinning
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// probe.ready and release.valid low
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class TileLinkIOWrapper extends TLModule {
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val io = new Bundle {
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val in = new UncachedTileLinkIO().flip
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val out = new TileLinkIO
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}
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io.out.acquire <> io.in.acquire
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io.out.grant <> io.in.grant
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io.out.finish <> io.in.finish
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io.out.probe.ready := Bool(true)
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io.out.release.valid := Bool(false)
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}
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// This version of TileLinkIO does not contain network headers for packets
|
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// that originate in the Clients (i.e. Acquire and Release). These headers
|
|
// are provided in the top-level that instantiates the clients and network.
|
|
// By eliding the header subbundles within the clients we can enable
|
|
// hierarchical P&R while minimizing unconnected port errors in GDS.
|
|
// Secondly, this version of the interface elides Finish messages, with the
|
|
// assumption that a FinishUnit has been coupled to the TileLinkIO port
|
|
// to deal with acking received Grants.
|
|
class HeaderlessUncachedTileLinkIO extends TLBundle {
|
|
val acquire = new DecoupledIO(new Acquire)
|
|
val grant = new DecoupledIO(new Grant).flip
|
|
}
|
|
|
|
class HeaderlessTileLinkIO extends HeaderlessUncachedTileLinkIO {
|
|
val probe = new DecoupledIO(new Probe).flip
|
|
val release = new DecoupledIO(new Release)
|
|
}
|
|
|
|
class HeaderlessTileLinkIOWrapper extends TLModule {
|
|
val io = new Bundle {
|
|
val in = new HeaderlessUncachedTileLinkIO().flip
|
|
val out = new HeaderlessTileLinkIO
|
|
}
|
|
io.out.acquire <> io.in.acquire
|
|
io.out.grant <> io.in.grant
|
|
io.out.probe.ready := Bool(true)
|
|
io.out.release.valid := Bool(false)
|
|
}
|
|
|
|
object TileLinkIOWrapper {
|
|
def apply(utl: HeaderlessUncachedTileLinkIO, p: Parameters): HeaderlessTileLinkIO = {
|
|
val conv = Module(new HeaderlessTileLinkIOWrapper)(p)
|
|
conv.io.in <> utl
|
|
conv.io.out
|
|
}
|
|
def apply(utl: HeaderlessUncachedTileLinkIO): HeaderlessTileLinkIO = {
|
|
val conv = Module(new HeaderlessTileLinkIOWrapper)
|
|
conv.io.in <> utl
|
|
conv.io.out
|
|
}
|
|
def apply(tl: HeaderlessTileLinkIO): HeaderlessTileLinkIO = tl
|
|
def apply(utl: UncachedTileLinkIO, p: Parameters): TileLinkIO = {
|
|
val conv = Module(new TileLinkIOWrapper)(p)
|
|
conv.io.in <> utl
|
|
conv.io.out
|
|
}
|
|
def apply(utl: UncachedTileLinkIO): TileLinkIO = {
|
|
val conv = Module(new TileLinkIOWrapper)
|
|
conv.io.in <> utl
|
|
conv.io.out
|
|
}
|
|
def apply(tl: TileLinkIO): TileLinkIO = tl
|
|
}
|
|
|
|
trait HasDataBeatCounters {
|
|
type HasBeat = TileLinkChannel with HasTileLinkBeatId
|
|
type HasClientId = TileLinkChannel with HasClientTransactionId
|
|
type LNAcquire = LogicalNetworkIO[Acquire]
|
|
type LNRelease = LogicalNetworkIO[Release]
|
|
type LNGrant = LogicalNetworkIO[Grant]
|
|
|
|
def connectDataBeatCounter[S <: TileLinkChannel : ClassTag](inc: Bool, data: S, beat: UInt) = {
|
|
val multi = data.hasMultibeatData()
|
|
val (multi_cnt, multi_done) = Counter(inc && multi, data.tlDataBeats)
|
|
val cnt = Mux(multi, multi_cnt, beat)
|
|
val done = Mux(multi, multi_done, inc)
|
|
(cnt, done)
|
|
}
|
|
|
|
def connectOutgoingDataBeatCounter[T <: Data : TypeTag](
|
|
in: DecoupledIO[T],
|
|
beat: UInt = UInt(0)): (UInt, Bool) = {
|
|
in.bits match {
|
|
case p: TileLinkChannel if typeTag[T].tpe <:< typeTag[TileLinkChannel].tpe =>
|
|
connectDataBeatCounter(in.fire(), p, beat)
|
|
case ln: LNGrant if typeTag[T].tpe <:< typeTag[LNGrant].tpe =>
|
|
connectDataBeatCounter(in.fire(), ln.payload, beat)
|
|
case _ => { require(false, "Don't know how to connect a beat counter to " + typeTag[T].tpe); (UInt(0), Bool(false))}
|
|
}
|
|
}
|
|
|
|
def connectIncomingDataBeatCounters[T <: HasClientId : ClassTag](
|
|
in: DecoupledIO[LogicalNetworkIO[T]],
|
|
entries: Int): Vec[Bool] = {
|
|
val id = in.bits.payload.client_xact_id
|
|
Vec((0 until entries).map { i =>
|
|
connectDataBeatCounter(in.fire() && id === UInt(i), in.bits.payload, UInt(0))._2
|
|
})
|
|
}
|
|
|
|
def connectIncomingDataBeatCounter[T <: Data : TypeTag](in: DecoupledIO[T]): Bool = {
|
|
in.bits match {
|
|
case p: TileLinkChannel if typeTag[T].tpe <:< typeTag[TileLinkChannel].tpe =>
|
|
connectDataBeatCounter(in.fire(), p, UInt(0))._2
|
|
case ln: LNAcquire if typeTag[T].tpe =:= typeTag[LNAcquire].tpe =>
|
|
connectDataBeatCounter(in.fire(), ln.payload, UInt(0))._2
|
|
case ln: LNRelease if typeTag[T].tpe =:= typeTag[LNRelease].tpe =>
|
|
connectDataBeatCounter(in.fire(), ln.payload, UInt(0))._2
|
|
case ln: LNGrant if typeTag[T].tpe =:= typeTag[LNGrant].tpe =>
|
|
connectDataBeatCounter(in.fire(), ln.payload, UInt(0))._2
|
|
case _ => { require(false, "Don't know how to connect a beat counter to " + typeTag[T].tpe); Bool(false)}
|
|
}
|
|
}
|
|
|
|
def connectHeaderlessTwoWayBeatCounter[ T <: TileLinkChannel : ClassTag, S <: TileLinkChannel : ClassTag](
|
|
max: Int,
|
|
up: DecoupledIO[T],
|
|
down: DecoupledIO[S],
|
|
beat: UInt): (Bool, UInt, Bool, UInt, Bool) = {
|
|
val cnt = Reg(init = UInt(0, width = log2Up(max+1)))
|
|
val (up_idx, do_inc) = connectDataBeatCounter(up.fire(), up.bits, beat)
|
|
val (down_idx, do_dec) = connectDataBeatCounter(down.fire(), down.bits, beat)
|
|
cnt := Mux(do_dec,
|
|
Mux(do_inc, cnt, cnt - UInt(1)),
|
|
Mux(do_inc, cnt + UInt(1), cnt))
|
|
(cnt > UInt(0), up_idx, do_inc, down_idx, do_dec)
|
|
}
|
|
|
|
def connectTwoWayBeatCounter[ T <: TileLinkChannel : ClassTag, S <: TileLinkChannel : ClassTag](
|
|
max: Int,
|
|
up: DecoupledIO[LogicalNetworkIO[T]],
|
|
down: DecoupledIO[LogicalNetworkIO[S]],
|
|
inc: T => Bool = (t: T) => Bool(true),
|
|
dec: S => Bool = (s: S) => Bool(true)): (Bool, UInt, Bool, UInt, Bool) = {
|
|
val cnt = Reg(init = UInt(0, width = log2Up(max+1)))
|
|
val (up_idx, up_done) = connectDataBeatCounter(up.fire(), up.bits.payload, UInt(0))
|
|
val (down_idx, down_done) = connectDataBeatCounter(down.fire(), down.bits.payload, UInt(0))
|
|
val do_inc = up_done && inc(up.bits.payload)
|
|
val do_dec = down_done && dec(down.bits.payload)
|
|
cnt := Mux(do_dec,
|
|
Mux(do_inc, cnt, cnt - UInt(1)),
|
|
Mux(do_inc, cnt + UInt(1), cnt))
|
|
(cnt > UInt(0), up_idx, up_done, down_idx, down_done)
|
|
}
|
|
}
|
|
|
|
class FinishQueueEntry extends TLBundle {
|
|
val fin = new Finish
|
|
val dst = UInt(width = log2Up(params(LNEndpoints)))
|
|
}
|
|
|
|
class FinishQueue(entries: Int) extends Queue(new FinishQueueEntry, entries)
|
|
|
|
class FinishUnit(srcId: Int = 0) extends TLModule
|
|
with HasDataBeatCounters {
|
|
val io = new Bundle {
|
|
val grant = Decoupled(new LogicalNetworkIO(new Grant)).flip
|
|
val refill = Decoupled(new Grant)
|
|
val finish = Decoupled(new LogicalNetworkIO(new Finish))
|
|
val ready = Bool(OUTPUT)
|
|
val grant_done = Bool(OUTPUT)
|
|
val pending_finish = Bool(OUTPUT)
|
|
}
|
|
|
|
val entries = 1 << tlClientXactIdBits
|
|
val g = io.grant.bits.payload
|
|
assert(g.client_xact_id <= UInt(entries), "No grant beat counter provisioned, only " + entries)
|
|
|
|
val done = connectIncomingDataBeatCounters(io.grant, entries).reduce(_||_)
|
|
val q = Module(new FinishQueue(entries))
|
|
|
|
q.io.enq.valid := io.grant.valid && g.requiresAck() && (!g.hasMultibeatData() || done)
|
|
q.io.enq.bits.fin := g.makeFinish()
|
|
q.io.enq.bits.dst := io.grant.bits.header.src
|
|
|
|
io.finish.bits.header.src := UInt(srcId)
|
|
io.finish.bits.header.dst := q.io.deq.bits.dst
|
|
io.finish.bits.payload := q.io.deq.bits.fin
|
|
io.finish.valid := q.io.deq.valid
|
|
q.io.deq.ready := io.finish.ready
|
|
|
|
io.refill.valid := io.grant.valid
|
|
io.refill.bits := io.grant.bits.payload
|
|
io.grant.ready := (q.io.enq.ready || !g.requiresAck()) && (io.refill.ready || !g.hasData())
|
|
|
|
io.ready := q.io.enq.ready
|
|
io.grant_done := done
|
|
io.pending_finish := q.io.deq.valid
|
|
}
|
|
|
|
object TileLinkHeaderOverwriter {
|
|
def apply[T <: ClientToManagerChannel](
|
|
in: DecoupledIO[LogicalNetworkIO[T]],
|
|
clientId: Int,
|
|
passThrough: Boolean): DecoupledIO[LogicalNetworkIO[T]] = {
|
|
val out = in.clone.asDirectionless
|
|
out.bits.payload := in.bits.payload
|
|
out.bits.header.src := UInt(clientId)
|
|
out.bits.header.dst := (if(passThrough) in.bits.header.dst else UInt(0))
|
|
out.valid := in.valid
|
|
in.ready := out.ready
|
|
out
|
|
}
|
|
|
|
def apply[T <: ClientToManagerChannel with HasCacheBlockAddress](
|
|
in: DecoupledIO[LogicalNetworkIO[T]],
|
|
clientId: Int,
|
|
nBanks: Int,
|
|
addrConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = {
|
|
val out: DecoupledIO[LogicalNetworkIO[T]] = apply(in, clientId, false)
|
|
out.bits.header.dst := addrConvert(in.bits.payload.addr_block)
|
|
out
|
|
}
|
|
|
|
def apply[T <: ClientToManagerChannel with HasCacheBlockAddress : ClassTag](
|
|
in: DecoupledIO[T],
|
|
clientId: Int,
|
|
addrConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = {
|
|
val out = new DecoupledIO(new LogicalNetworkIO(in.bits.clone)).asDirectionless
|
|
out.bits.payload := in.bits
|
|
out.bits.header.src := UInt(clientId)
|
|
out.bits.header.dst := addrConvert(in.bits.addr_block)
|
|
out.valid := in.valid
|
|
in.ready := out.ready
|
|
out
|
|
}
|
|
}
|
|
|
|
class TileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt) extends TLModule {
|
|
val io = new Bundle {
|
|
val client = new HeaderlessTileLinkIO().flip
|
|
val network = new TileLinkIO
|
|
}
|
|
|
|
val finisher = Module(new FinishUnit(clientId))
|
|
finisher.io.grant <> io.network.grant
|
|
io.network.finish <> finisher.io.finish
|
|
|
|
val acq_with_header = TileLinkHeaderOverwriter(io.client.acquire, clientId, addrConvert)
|
|
val rel_with_header = TileLinkHeaderOverwriter(io.client.release, clientId, addrConvert)
|
|
val prb_without_header = DecoupledLogicalNetworkIOUnwrapper(io.network.probe)
|
|
val gnt_without_header = finisher.io.refill
|
|
|
|
io.network.acquire.bits := acq_with_header.bits
|
|
io.network.acquire.valid := acq_with_header.valid && finisher.io.ready
|
|
acq_with_header.ready := io.network.acquire.ready && finisher.io.ready
|
|
io.network.release <> rel_with_header
|
|
io.client.probe <> prb_without_header
|
|
io.client.grant <> gnt_without_header
|
|
}
|
|
|
|
object TileLinkNetworkPort {
|
|
def apply[T <: Data](
|
|
client: HeaderlessTileLinkIO,
|
|
clientId: Int = 0,
|
|
addrConvert: UInt => UInt = u => UInt(0))(implicit p: Parameters): TileLinkIO = {
|
|
val port = Module(new TileLinkNetworkPort(clientId, addrConvert))(p)
|
|
port.io.client <> client
|
|
port.io.network
|
|
}
|
|
}
|
|
|
|
class TileLinkEnqueuer(depths: (Int, Int, Int, Int, Int)) extends Module {
|
|
val io = new Bundle {
|
|
val client = new TileLinkIO().flip
|
|
val manager = new TileLinkIO
|
|
}
|
|
io.manager.acquire <> (if(depths._1 > 0) Queue(io.client.acquire, depths._1) else io.client.acquire)
|
|
io.client.probe <> (if(depths._2 > 0) Queue(io.manager.probe, depths._2) else io.manager.probe)
|
|
io.manager.release <> (if(depths._3 > 0) Queue(io.client.release, depths._3) else io.client.release)
|
|
io.client.grant <> (if(depths._4 > 0) Queue(io.manager.grant, depths._4) else io.manager.grant)
|
|
io.manager.finish <> (if(depths._5 > 0) Queue(io.client.finish, depths._5) else io.client.finish)
|
|
}
|
|
|
|
object TileLinkEnqueuer {
|
|
def apply(in: TileLinkIO, depths: (Int, Int, Int, Int, Int))(p: Parameters): TileLinkIO = {
|
|
val t = Module(new TileLinkEnqueuer(depths))(p)
|
|
t.io.client <> in
|
|
t.io.manager
|
|
}
|
|
def apply(in: TileLinkIO, depth: Int)(p: Parameters): TileLinkIO = {
|
|
apply(in, (depth, depth, depth, depth, depth))(p)
|
|
}
|
|
}
|
|
|
|
abstract trait HasArbiterTypes {
|
|
type ManagerSourcedWithId = ManagerToClientChannel with HasClientTransactionId
|
|
type ClientSourcedWithId = ClientToManagerChannel with HasClientTransactionId
|
|
type ClientSourcedWithIdAndData = ClientToManagerChannel with
|
|
HasClientTransactionId with
|
|
HasTileLinkData
|
|
}
|
|
|
|
// Utility functions for constructing TileLinkIO arbiters
|
|
trait TileLinkArbiterLike extends HasArbiterTypes with TileLinkParameters{
|
|
val arbN: Int
|
|
// These are filled in depending on whether the arbiter mucks with the
|
|
// client ids and then needs to revert them on the way back
|
|
def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int): Bits
|
|
def managerSourcedClientXactId(in: ManagerSourcedWithId): Bits
|
|
def arbIdx(in: ManagerSourcedWithId): UInt
|
|
|
|
def hookupClientSource[M <: ClientSourcedWithIdAndData : ClassTag](
|
|
clts: Seq[DecoupledIO[LogicalNetworkIO[M]]],
|
|
mngr: DecoupledIO[LogicalNetworkIO[M]]) {
|
|
def hasData(m: LogicalNetworkIO[M]) = m.payload.hasMultibeatData()
|
|
val arb = Module(new LockingRRArbiter(mngr.bits.clone, arbN, tlDataBeats, Some(hasData _)))
|
|
clts.zipWithIndex.zip(arb.io.in).map{ case ((req, id), arb) => {
|
|
arb.valid := req.valid
|
|
arb.bits := req.bits
|
|
arb.bits.payload.client_xact_id := clientSourcedClientXactId(req.bits.payload, id)
|
|
req.ready := arb.ready
|
|
}}
|
|
arb.io.out <> mngr
|
|
}
|
|
|
|
def hookupClientSourceHeaderless[M <: ClientSourcedWithIdAndData : ClassTag](
|
|
clts: Seq[DecoupledIO[M]],
|
|
mngr: DecoupledIO[M]) {
|
|
def hasData(m: M) = m.hasMultibeatData()
|
|
val arb = Module(new LockingRRArbiter(mngr.bits.clone, arbN, tlDataBeats, Some(hasData _)))
|
|
clts.zipWithIndex.zip(arb.io.in).map{ case ((req, id), arb) => {
|
|
arb.valid := req.valid
|
|
arb.bits := req.bits
|
|
arb.bits.client_xact_id := clientSourcedClientXactId(req.bits, id)
|
|
req.ready := arb.ready
|
|
}}
|
|
arb.io.out <> mngr
|
|
}
|
|
|
|
def hookupManagerSourceWithHeader[M <: ManagerToClientChannel](
|
|
clts: Seq[DecoupledIO[LogicalNetworkIO[M]]],
|
|
mngr: DecoupledIO[LogicalNetworkIO[M]]) {
|
|
mngr.ready := Bool(false)
|
|
for (i <- 0 until arbN) {
|
|
clts(i).valid := Bool(false)
|
|
when (mngr.bits.header.dst === UInt(i)) {
|
|
clts(i).valid := mngr.valid
|
|
mngr.ready := clts(i).ready
|
|
}
|
|
clts(i).bits := mngr.bits
|
|
}
|
|
}
|
|
|
|
def hookupManagerSourceWithId[M <: ManagerSourcedWithId](
|
|
clts: Seq[DecoupledIO[LogicalNetworkIO[M]]],
|
|
mngr: DecoupledIO[LogicalNetworkIO[M]]) {
|
|
mngr.ready := Bool(false)
|
|
for (i <- 0 until arbN) {
|
|
clts(i).valid := Bool(false)
|
|
when (arbIdx(mngr.bits.payload) === UInt(i)) {
|
|
clts(i).valid := mngr.valid
|
|
mngr.ready := clts(i).ready
|
|
}
|
|
clts(i).bits := mngr.bits
|
|
clts(i).bits.payload.client_xact_id := managerSourcedClientXactId(mngr.bits.payload)
|
|
}
|
|
}
|
|
|
|
def hookupManagerSourceHeaderlessWithId[M <: ManagerSourcedWithId](
|
|
clts: Seq[DecoupledIO[M]],
|
|
mngr: DecoupledIO[M]) {
|
|
mngr.ready := Bool(false)
|
|
for (i <- 0 until arbN) {
|
|
clts(i).valid := Bool(false)
|
|
when (arbIdx(mngr.bits) === UInt(i)) {
|
|
clts(i).valid := mngr.valid
|
|
mngr.ready := clts(i).ready
|
|
}
|
|
clts(i).bits := mngr.bits
|
|
clts(i).bits.client_xact_id := managerSourcedClientXactId(mngr.bits)
|
|
}
|
|
}
|
|
|
|
def hookupManagerSourceBroadcast[M <: Data](
|
|
clts: Seq[DecoupledIO[M]],
|
|
mngr: DecoupledIO[M]) {
|
|
clts.map{ _.valid := mngr.valid }
|
|
clts.map{ _.bits := mngr.bits }
|
|
mngr.ready := clts.map(_.ready).reduce(_&&_)
|
|
}
|
|
|
|
def hookupFinish[M <: LogicalNetworkIO[Finish] : ClassTag](
|
|
clts: Seq[DecoupledIO[M]],
|
|
mngr: DecoupledIO[M]) {
|
|
val arb = Module(new RRArbiter(mngr.bits.clone, arbN))
|
|
arb.io.in zip clts map { case (arb, req) => arb <> req }
|
|
arb.io.out <> mngr
|
|
}
|
|
}
|
|
|
|
abstract class UncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike {
|
|
val io = new Bundle {
|
|
val in = Vec.fill(arbN){new UncachedTileLinkIO}.flip
|
|
val out = new UncachedTileLinkIO
|
|
}
|
|
hookupClientSource(io.in.map(_.acquire), io.out.acquire)
|
|
hookupFinish(io.in.map(_.finish), io.out.finish)
|
|
hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
|
|
}
|
|
|
|
abstract class TileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike {
|
|
val io = new Bundle {
|
|
val in = Vec.fill(arbN){new TileLinkIO}.flip
|
|
val out = new TileLinkIO
|
|
}
|
|
hookupClientSource(io.in.map(_.acquire), io.out.acquire)
|
|
hookupClientSource(io.in.map(_.release), io.out.release)
|
|
hookupFinish(io.in.map(_.finish), io.out.finish)
|
|
hookupManagerSourceBroadcast(io.in.map(_.probe), io.out.probe)
|
|
hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
|
|
}
|
|
|
|
class HeaderlessUncachedTileLinkIOArbiter(val arbN: Int) extends Module
|
|
with TileLinkArbiterLike
|
|
with AppendsArbiterId {
|
|
val io = new Bundle {
|
|
val in = Vec.fill(arbN){new HeaderlessUncachedTileLinkIO}.flip
|
|
val out = new HeaderlessUncachedTileLinkIO
|
|
}
|
|
hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
|
|
hookupManagerSourceHeaderlessWithId(io.in.map(_.grant), io.out.grant)
|
|
}
|
|
|
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class HeaderlessTileLinkIOArbiter(val arbN: Int) extends Module
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with TileLinkArbiterLike
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with AppendsArbiterId {
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val io = new Bundle {
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val in = Vec.fill(arbN){new HeaderlessTileLinkIO}.flip
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val out = new HeaderlessTileLinkIO
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}
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hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
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hookupClientSourceHeaderless(io.in.map(_.release), io.out.release)
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hookupManagerSourceBroadcast(io.in.map(_.probe), io.out.probe)
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hookupManagerSourceHeaderlessWithId(io.in.map(_.grant), io.out.grant)
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}
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// Appends the port index of the arbiter to the client_xact_id
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trait AppendsArbiterId extends TileLinkArbiterLike {
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def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) =
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Cat(in.client_xact_id, UInt(id, log2Up(arbN)))
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def managerSourcedClientXactId(in: ManagerSourcedWithId) =
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in.client_xact_id >> UInt(log2Up(arbN))
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def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0).toUInt
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}
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// Uses the client_xact_id as is (assumes it has been set to port index)
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trait PassesId extends TileLinkArbiterLike {
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def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) = in.client_xact_id
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def managerSourcedClientXactId(in: ManagerSourcedWithId) = in.client_xact_id
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def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id
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}
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// Overwrites some default client_xact_id with the port idx
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trait UsesNewId extends TileLinkArbiterLike {
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def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) = UInt(id, log2Up(arbN))
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def managerSourcedClientXactId(in: ManagerSourcedWithId) = UInt(0)
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def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id
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}
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// Mix-in id generation traits to make concrete arbiter classes
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class UncachedTileLinkIOArbiterThatAppendsArbiterId(val n: Int) extends UncachedTileLinkIOArbiter(n) with AppendsArbiterId
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class UncachedTileLinkIOArbiterThatPassesId(val n: Int) extends UncachedTileLinkIOArbiter(n) with PassesId
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class UncachedTileLinkIOArbiterThatUsesNewId(val n: Int) extends UncachedTileLinkIOArbiter(n) with UsesNewId
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class TileLinkIOArbiterThatAppendsArbiterId(val n: Int) extends TileLinkIOArbiter(n) with AppendsArbiterId
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class TileLinkIOArbiterThatPassesId(val n: Int) extends TileLinkIOArbiter(n) with PassesId
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class TileLinkIOArbiterThatUsesNewId(val n: Int) extends TileLinkIOArbiter(n) with UsesNewId
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