riscv/rocket-chip
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Author SHA1 Message Date
Henry CookandGitHub f9acd4988c Merge pull request #551 from edwardcwang/configdoc 
Update config override documentation
 2017-02-09 11:56:38 -08:00
Henry CookandGitHub fc7838ff7b Merge branch 'master' into configdoc 2017-02-09 10:09:30 -08:00
Henry CookandGitHub fbefbb5549 Merge pull request #552 from ucb-bar/fix-abs-func 
Fix up Absolute value.
 2017-02-09 10:09:16 -08:00
Henry CookandGitHub b567a2a356 Merge pull request #536 from ucb-bar/diplomacy-star-nodes 
diplomacy: add :*= and :=* to support flexible # of edges
 2017-01-30 11:19:33 -08:00
Henry CookandGitHub 0fe2899c74 [tracegen] remove TL1 noisemaker, use io.finish and catch simulation exit (#528) 2017-01-25 12:10:49 -08:00
Henry Cook e03ba637f4 [regression] remove FancyMemTest (timing out) 2017-01-19 17:48:04 -08:00
Henry Cook c1b7c84f09 [rocket] bugfix: RoccExampleConfig looks up PAddrBits too early 2017-01-19 17:48:04 -08:00
Henry Cook e0411c6cde [coreplex] bugfix: re-enable multicore configs via WithNCores 2017-01-19 17:48:04 -08:00
Henry Cook 307f938b88 [rocket] bugfix: fixes #517 2017-01-19 17:48:04 -08:00
Henry CookandGitHub 1b31dfa700 Update sbt to 13.12 (#514) 
Closes #496
 2017-01-17 16:26:22 -08:00
Henry CookandGitHub 9a6634cd40 Add TLBuffers on the L1 backends and blind exit points (#513) 
* [coreplex] add TLBuffers on the exit points from the Tile and Coreplex
* [config] WithBootROMFile
 2017-01-17 11:57:23 -08:00
Henry CookandGitHub 74b6a8d02b Refactor Tile to use cake pattern (#502) 
* [rocket] Refactor Tile into cake pattern with traits
* [rocket] cacheDataBits &etc in HasCoreParameters
* [rocket] pass TLEdgeOut implicitly rather than relying on val edge in HasCoreParameters
* [rocket] frontend and icache now diplomatic
* [rocket] file name capitalization
* [rocket] re-add hook for inserting externally-defined Cores
* [rocket] add FPUCoreIO
* [groundtest] move TL1 Config instances to where they are used
* [unittest] remove legacy unit tests
* [groundtest] remove legacy device tests
 2017-01-16 18:24:08 -08:00
Henry Cook a8ee7e0678 Update README 2016-11-28 16:10:50 -08:00
Henry Cook 86065e5fb8 Merge remote-tracking branch 'origin/master' into bump-submodules 2016-11-28 13:49:59 -08:00
Henry Cook 837d207064 [travis] split up groundtest into two suites 2016-11-23 12:27:40 -08:00
Henry Cook 38c5af5bad [rocket] cleanup mshr logic 2016-11-23 12:09:56 -08:00
Henry Cook dae6772624 factor out common cache subcomponents into uncore.util 2016-11-23 12:09:35 -08:00
Henry Cook 16d0f522b0 [tracegen] filter seed report 2016-11-23 12:09:09 -08:00
Henry Cook c65c255815 [coreplex] TileId moved to groundtest 2016-11-23 12:08:45 -08:00
Henry Cook 28c6be90ab [rocket] require refillcycesperbeat == 1 and remove flowthroughserializer 2016-11-20 19:36:51 -08:00
Henry Cook ff9b5bf8fc [rocket] nbdcache release bugfix 2016-11-20 19:07:06 -08:00
Henry Cook e68795421a remove L2 regressions for now 2016-11-19 20:11:20 -08:00
Henry Cook 3f47d5b5eb [rocket] re-enable working NBDcache (passes Tracegen) 2016-11-19 19:19:16 -08:00
Henry Cook c31b41a7ac [tl2] add grant finisher comment 2016-11-19 19:16:43 -08:00
Henry Cook 2976fd84e4 [rocket] resolve cde/config conflicts 2016-11-18 19:11:34 -08:00
Henry Cook 8b908465e0 [tl2] convert NBDcache to TL2 (WIP; compiles but untested) 2016-11-18 19:04:06 -08:00
Henry Cook 5f1cc19d71 [tl2] fix comment explaining permissions 2016-11-18 19:02:17 -08:00
Henry Cook 10112da4e7 [tl2] won't need putthrough opcode 2016-11-18 19:02:17 -08:00
Henry Cook 5bd343bac8 [rocket] d_last && d.fire() => d_done 2016-11-17 18:42:59 -08:00
Henry Cook 1ddccb1b33 [rocket] add TODO for single cycle ack 2016-11-17 18:42:59 -08:00
Henry Cook 94086f2270 [tl2] broadcast hub probe port width bugfix 2016-11-17 18:42:59 -08:00
Henry Cook 960c2723ab [tl2] MemoryOpCategories: use def to supply Cat'd consts 2016-11-17 18:42:59 -08:00
Henry Cook 92e233d596 [groundtest] testramaddr constant in package 2016-11-16 18:42:56 -08:00
Henry Cook e1992d7c55 [rocket] grant addr bugfix 2016-11-16 18:12:06 -08:00
Henry Cook 84f249bd03 [rocketchip] BigInt cast 2016-11-16 18:11:06 -08:00
Henry Cook da7ecfd189 [rocket] probeack vs probeackdata bugfix 2016-11-16 17:27:02 -08:00
Henry Cook 75d4347192 [groundtest] runs tests with new coreplex and top 2016-11-16 17:05:53 -08:00
Henry Cook 24e3216fcf coreplex: allow zero interrupt sink/sources 2016-11-16 16:50:36 -08:00
Henry Cook 479bc82f03 tilelink2 Broadcast: improve bufferless throughput 2016-11-16 16:50:36 -08:00
Henry Cook 408e78e35e rocketchip Periphery: ExtMem and ExtBus Configs 2016-11-16 16:50:30 -08:00
Henry Cook 1f51564577 [rocket] dcache probe ack data bugfix 2016-11-16 14:25:21 -08:00
Henry Cook 66a2c5544e [rocket] L1D acquire addr bugfix 2016-11-16 13:38:52 -08:00
Henry Cook c5e03c9c76 [rocket] dcache release addr bugfix 2016-11-16 13:14:51 -08:00
Henry Cook 2d68f12115 [tl2] give groundtest tile some output nodes 2016-11-14 18:09:40 -08:00
Henry Cook 0e30364f56 WIP 2016-11-14 13:39:01 -08:00
Henry Cook c0efd247b0 [tl2] expand firstlast api and L1WB bugfix 2016-11-14 12:12:31 -08:00
Henry Cook b7730d66f2 WIP bugfixes: run until corrupted WB data (beats repeated) 2016-11-11 18:34:48 -08:00
Henry Cook 71315d5cf5 WIP scala compile and firrtl elaborate; monitor error 2016-11-11 13:07:45 -08:00
Henry Cook afa1a6d549 WIP uncore and rocket changes compile 2016-11-10 15:57:29 -08:00
Henry CookandHenry Cook 7bca99a27a [tilelink2] Add unit test configs to regression 2016-09-28 18:02:04 -07:00
Henry CookandHenry Cook 32f3f94882 [tilelink2] Fix zero-width wires in RAMModel. 2016-09-28 18:02:04 -07:00
Henry CookandHenry Cook 69e121260e [tilelink2] Add unit tests for many TL2 components 
These tests mostly use the Fuzzer and RAMModel to check that adapters
correctly handle randomly generated legal traffic.
 2016-09-28 18:02:04 -07:00
Henry Cook 1e54820f8c Merge remote-tracking branch 'origin/master' into unittest-config 2016-09-22 16:03:51 -07:00
Henry Cook 411ee378de Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages. 2016-09-22 15:59:29 -07:00
Henry Cook 83c08a931d [WIP] Generators for unittest and groundtest; disambiguate groundtest.TrafficGenerator 2016-09-22 14:57:18 -07:00
Henry Cook 47c5d1a992 [WIP] Move RocketTestSuite generation into RocketchipGenerator 2016-09-22 14:31:45 -07:00
Henry Cook 64fe010369 [unittest] Config import tweaks 2016-09-21 17:40:39 -07:00
Henry Cook fd5e00fed9 [coreplex] rename Testing.scala -> RocketTestSuite.scala 2016-09-21 17:35:39 -07:00
Henry Cook 270011b768 [unittest] more Config cleanup 2016-09-21 17:30:14 -07:00
Henry Cook 40f6f31611 [unittest] further refactor unittest framework 2016-09-20 14:14:30 -07:00
Henry Cook ed91e9a89b Merge remote-tracking branch 'origin' into testharness-refactor 2016-09-20 13:03:21 -07:00
Henry Cook b97a0947a9 [rocketchip] enable piecewise Generator output 2016-09-20 12:57:56 -07:00
Henry Cook 2961d92244 [testharness] vsim makefrag cleanup 2016-09-19 15:14:45 -07:00
Henry Cook df442ed82c [rocketchip] avoid pending merge conflict] 2016-09-19 13:24:01 -07:00
Henry Cook ddcf1b4099 Use PROJECT rather than MODEL in name of binary and generated src files. 2016-09-19 13:23:17 -07:00
Henry Cook 7b8aa6c839 [rocketchip] split out Base and Example tops 2016-09-19 11:00:13 -07:00
Henry Cook 851a336db4 [unittest] split out Config and TestHarness into separate files, minimize imports 2016-09-15 14:25:47 -07:00
Henry Cook 245f8ab76b [util] move LatencyPipe into util 2016-09-15 13:30:34 -07:00
Henry Cook a70d8c9821 Merge remote-tracking branch 'origin/master' into testharness-refactor 2016-09-15 13:27:07 -07:00
Henry Cook be9ddae77f make groundtest and unitest peers of rocketchip, with their own packages, harnesses and configs 2016-09-15 13:04:01 -07:00
Henry Cook c6f252a913 Remove Option from success flag in coreplex; just use a sane default. 2016-09-15 12:19:22 -07:00
Henry Cook 9e2b0aad65 Revert "allow MODEL to be something other than TestHarness" 
This reverts commit bf253aaa97.
 2016-09-15 11:53:05 -07:00
Henry Cook 888f6a2a55 Revert "move UnitTest back into rocketchip module" 
This reverts commit f95b8c4ec2.
 2016-09-15 11:48:09 -07:00
Henry CookandHoward Mao cde104b3fa [junctions] Removes the obsoleted SMI. 
Closes #280.
 2016-09-14 20:06:22 -07:00
Henry Cook 1b53e477fa Merge branch 'master' of github.com:ucb-bar/rocket-chip into tl2-irrevocable 2016-09-14 17:50:17 -07:00
Henry Cook e02d149cbe [tilelink2] Convert TileLink2 to use IrrevocableIO. Add checks to the Monitor to enforce Irrevocable semantics on TLEdges. Update the RegisterRouterTests to pass the new Monitor assertions. 2016-09-14 17:43:07 -07:00
Henry Cook 3030718f72 bump chisel3 2016-09-14 17:40:22 -07:00
Henry Cook 08c4c7b985 [junctions] make async crossings capable of providing IrrevocableIO 2016-09-14 17:38:54 -07:00
Henry Cook aa3fa90fe3 [tilelink2] Monitor: miscopied name in assert message 2016-09-14 14:56:50 -07:00
Henry Cook d76e19a6ab [tilelink2] Monitor: simplify monitor interface. EdgeIn and EdgeOut are required to be the same, so why pass around both? 2016-09-14 14:23:23 -07:00
Henry CookandHoward Mao 7dd4492abb First cut at refactoring unittests into a top-level utility. Individual tests co-located with their DUT. No functional changes. 2016-09-13 20:30:14 -07:00
Henry Cook e318c29d48 [tilelink2] Fuzzer: Allow noise-making to be parameterized. Better comments. 2016-09-13 12:25:57 -07:00
Henry Cook 05100c12a7 Merge branch 'master' of github.com:ucb-bar/rocket-chip into monitor 2016-09-13 11:18:18 -07:00
Henry Cook ad8e563c89 [tilelink2] Fuzzer: Rewrite of fuzzer 
Multiple bug-fixes and actual source id generation.
 2016-09-12 17:00:58 -07:00
Henry Cook 0b0c891179 [tilelink2] Monitor: Allow zero-mask PutPartials 
this will require a larger address refactoring TBD
 2016-09-12 17:00:50 -07:00
Henry Cook c57b52ec86 tilelink2 Fragmenter: bugfix using D.hasData 2016-09-12 16:58:21 -07:00
Henry Cook 82681179cb [tilelink2] Edges: add size to addr_lo. 
addr_lo cannot correctly be deciphered from the mask alone.
OxC still has addr_lo === 0 if size is >1.
 2016-09-12 16:58:09 -07:00
Henry Cook a21b04a7c1 playground for making different DAGs to use as DUTs 2016-09-12 10:32:45 -07:00
Henry Cook 0671d5d637 Initial version of fuzzer and simple ram fuzz test 2016-09-12 10:32:45 -07:00
Henry CookandHoward Mao e406d1bd73 Make probeCopy have same behavior as probeDowngrade 2016-07-18 18:22:49 -07:00