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Commit Graph

650 Commits

Author SHA1 Message Date
Andrew Waterman
50a283d311 move store data generation into EX stage
doing so removes it from the critical path of FP store unrecoding.
2012-02-12 01:35:55 -08:00
Andrew Waterman
725190d0ee update to new chisel 2012-02-11 17:20:33 -08:00
Andrew Waterman
f8b937d590 fix 32-bit divider bug
thanks, torture!

also, tidied up the code a bit.
2012-02-09 03:47:59 -08:00
Andrew Waterman
03ee49f424 fix 32-bit AMOs to upper halves of 64-bit words
thanks, torture!
2012-02-09 03:31:47 -08:00
Yunsup Lee
f47d888feb vvcfgivl and vsetvl works 2012-02-09 02:35:21 -08:00
Andrew Waterman
92493ad153 fix mul/div kill bug
occasionally, an in-progress multiply or divide could be
erroneously killed, tying up the register forever.
2012-02-09 02:26:03 -08:00
Andrew Waterman
128ec567ed make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux.  the benfit
was close to nil, anyway.
2012-02-09 01:34:00 -08:00
Yunsup Lee
fcc8081c4d hook up the vector command queue 2012-02-09 01:28:16 -08:00
Andrew Waterman
8b6b0f5367 add external memory request interface for vec unit 2012-02-08 22:30:45 -08:00
Yunsup Lee
9285a52f25 initial vu integration 2012-02-08 21:43:45 -08:00
Andrew Waterman
10b5a0006c fix mul/div to rd=0 2012-02-08 20:11:57 -08:00
Andrew Waterman
a1855b12c2 clean up queues 2012-02-08 17:55:05 -08:00
Andrew Waterman
990e3a1b34 fix fpu port direction bug 2012-02-08 15:19:26 -08:00
Andrew Waterman
b3f6f9a5fd fix BTB misprediction check for negative addresses
also index BTB with PC, not PC+4
2012-02-08 15:05:28 -08:00
Andrew Waterman
e9da2cf66a improve id/ex datapath
move operand selection into decode stage; simplify bypassing
2012-02-08 06:47:26 -08:00
Andrew Waterman
d471a8b2da arbitrate for LLFU writebacks in MEM stage 2012-02-08 04:21:05 -08:00
Andrew Waterman
ebed56500e fix mul/wb hazard checks
I erroneously assumed that those instructions set id_wen.
2012-02-08 01:56:11 -08:00
Andrew Waterman
5403d069e9 add fp loads/stores 2012-02-07 23:54:25 -08:00
Christopher Celio
1be9d15944 Fixed bug regarding case sensitivity regarding ioICache,ioDCache 2012-02-07 14:07:42 -08:00
Andrew Waterman
fde8e3b696 clean up bypassing/hazard checking a bit 2012-02-06 17:26:45 -08:00
Henry Cook
41c4e10c37 Workaround for another frakking extraction error in the C backend. C and VLSI backends now both boot kernel with associativity on 2012-02-02 21:53:57 -08:00
Andrew Waterman
99a959e6b1 remove pc+4 piperegs and add new ex pc+4 adder 2012-02-02 13:33:27 -08:00
Andrew Waterman
01a156eb98 make # of dcache lines configurable 2012-02-01 21:11:45 -08:00
Andrew Waterman
b1bbf56b74 clean up wb->id bypass 2012-02-01 16:41:18 -08:00
Henry Cook
c5a4eaa0a1 Associative cache, boots kernel 2012-02-01 13:26:04 -08:00
Henry Cook
281abfbccb New Mux1H constructor 2012-02-01 13:24:28 -08:00
Andrew Waterman
38c9105ea1 fix mul/div deadlock bug
If independent multiplies or independent divides were issued
back-to-back, the second wouldn't execute, causing the register
to be busy forever.
2012-01-30 21:14:28 -08:00
Andrew Waterman
bd241ea237 fix when badvaddr is set 2012-01-30 17:15:42 -08:00
Andrew Waterman
a96c92f58d enable amomin[u]/amomax[u 2012-01-26 20:45:04 -08:00
Andrew Waterman
a7999d4525 don't flush I$ unless fence.i commits
otherwise, we might not make forward progress.
2012-01-26 20:37:09 -08:00
Andrew Waterman
32f5f420f3 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-01-26 20:12:42 -08:00
Andrew Waterman
41855a6d47 fix missing "otherwise" in PCR file
this fixes timer interrupts for VLSI backend.
2012-01-26 19:33:55 -08:00
Andrew Waterman
7172ddd050 don't flush pipeline after MFPCR 2012-01-24 18:40:08 -08:00
Andrew Waterman
97c379f1d7 made I$ associative 2012-01-24 16:51:30 -08:00
Henry Cook
aa3465699b LFSR now a util 2012-01-24 15:26:19 -08:00
Andrew Waterman
7f26fe2c44 make icache size parameterizable 2012-01-24 15:13:49 -08:00
Henry Cook
8229d65adf Associative cache passes asm tests and bmarks with power of 2 associativities (including 1) 2012-01-24 11:41:44 -08:00
Andrew Waterman
9e6b86fe85 Fix a nasty replay bug
If a mispredicted branch was followed by an instruction dependent
on a load that missed in the cache, the mispredicted path would
be executed rather than the correct path. Fail.

Example broken code:

lw   x2, 0(x2)          # cache miss
beq  x3, x0, somewhere  # mispredicted branch
move x4, x2             # wrong-path instruction dependent on load miss
2012-01-24 03:40:01 -08:00
Andrew Waterman
06fdf79dab fix long-latency writeback arbitration bug 2012-01-24 00:56:47 -08:00
Andrew Waterman
f1c355e3cd check pc/effective address sign extension 2012-01-24 00:15:17 -08:00
Andrew Waterman
a5a020f97b update chisel and remove SRAM_READ_LATENCY 2012-01-23 20:59:38 -08:00
Henry Cook
8766438bb9 Updated chisel removes ^^ from language. Removed from rocket source, updated jar. 2012-01-23 17:09:23 -08:00
Andrew Waterman
e7bf07d55e fix AMO replay bug 2012-01-23 15:35:53 -08:00
Andrew Waterman
d59bddfbf1 fix I$ miss replay bug 2012-01-21 20:42:13 -08:00
Andrew Waterman
31c56228e2 add missing "otherwise" 2012-01-21 20:13:15 -08:00
Henry Cook
97f0852b17 DM cache with assoc-aware subunits passes all asm and bmarks 2012-01-18 17:53:26 -08:00
Henry Cook
8623d58724 split into two caches, compiles 2012-01-18 17:09:35 -08:00
Henry Cook
29ed8eb31a More utils for nbdcache 2012-01-18 17:09:35 -08:00
Henry Cook
7e25749581 Groundwork for assoc cache implementation 2012-01-18 17:09:35 -08:00
Andrew Waterman
07f184df2f adhere to new chisel c naming convention 2012-01-18 15:23:21 -08:00