riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
532 Commits 1 Branch 0 Tags 13 MiB
ebf2417a32
Commit Graph

532 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Howard Mao
eb62ff6a50 add queues between Nasti -> TL converter and Nasti interconnect 2015-10-26 14:15:25 -07:00
Howard Mao
f37938e4de implement MultiChannel routing 2015-10-26 14:15:25 -07:00
Yunsup Lee
a175afae73 make ZscaleChip work with new parameters framework 2015-10-25 10:24:39 -07:00
Howard Mao
c3a7dcf0ab fix missing cde library dependencies in submodules 2015-10-23 15:05:19 -07:00
Colin Schmidt
854feab08e add knob and constraint dumping 2015-10-22 17:25:38 -07:00
Henry Cook
9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
Henry Cook
47bc193c16 added CDE library as submodule 2015-10-21 18:24:16 -07:00
Howard Mao
21f342ad42 fix typo causing L2 cache configuration to fail 2015-10-21 13:37:33 -07:00
Howard Mao
d5a75fd113 accidentally committed some code I didn't mean to in Rocket 2015-10-21 09:21:54 -07:00
Howard Mao
693a4ae00e fix some more memory system bugs 2015-10-20 23:29:59 -07:00
Howard Mao
c311c9938e nitpicky declaration move 2015-10-20 21:10:54 -07:00
Henry Cook
62765e9609 L2 rowBits param bugfix 2015-10-20 18:57:19 -07:00
Henry Cook
3fc630405b Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale) 2015-10-20 15:05:12 -07:00
Howard Mao
4346111d2a fix remaining vsim harness typo 2015-10-19 20:20:14 -07:00
Howard Mao
896aa892d1 bump uncore for TL -> NASTI converter fix 2015-10-19 15:31:59 -07:00
Henry Cook
8c3370c2e3 L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale) 2015-10-16 19:15:47 -07:00
Howard Mao
c4117eb9a2 make sure TL parameters change properly throughout 
* Outermost TL parameters should have the width set to be the same as the
   MIF data width.
 * Broadcast Hub and Narrower, which use different sets of TL parameters
   should use the proper set of parameters at each interface
 2015-10-14 18:03:39 -07:00
Henry Cook
4270fd78a5 Merge branch 'param-refactor-tl' 2015-10-14 12:16:22 -07:00
Henry Cook
dd5052888d refactor tilelink params, compiles but ExampleSmallConfig fails 2015-10-13 23:44:05 -07:00
Howard Mao
a44e054c77 add support for different TileLink and MIF data widths 2015-10-13 12:46:23 -07:00
Henry Cook
9d11b64c75 added HasAddrMapParameters and GlobalAddrMap 2015-10-06 18:24:08 -07:00
Henry Cook
1c489d75c1 inject params at top-level for MemDessert 2015-10-06 16:26:58 -07:00
Henry Cook
c4eadbda57 Removed all traces of params 2015-10-06 11:42:06 -07:00
Henry Cook
38ae2707a3 refactor MemIO to not use params 2015-10-06 11:41:48 -07:00
Henry Cook
3d10a89907 refactor NASTI to not use param; new AddrMap class 2015-10-06 11:41:47 -07:00
Andrew Waterman
c2ad0b7dd4 Unfuck fpga-zynq submodule pointer 
Sorry, Scott.
 2015-10-01 15:00:35 -07:00
Andrew Waterman
996670a4a6 Point to correct Chisel commit 2015-10-01 10:31:29 -07:00
Howard Mao
a76f0bf8fb fix involuntary release bug in rocket ProbeUnit 2015-09-30 17:26:48 -07:00
Andrew Waterman
8da7be3211 More Chisel3 compatibility fixes 2015-09-30 14:37:40 -07:00
Andrew Waterman
79cdf6efc0 Make perf counters optional 2015-09-28 13:56:08 -07:00
Howard Mao
353b00c8a1 revert some Chisel3-related changes and fix tlb bugs 2015-09-26 22:08:06 -07:00
Howard Mao
c517d9f6e3 fix htif emulator constructor in vcs_main 2015-09-25 17:21:09 -07:00
Howard Mao
7b0167b92e make sure SCR and PCR data width matches xLen 2015-09-25 12:13:22 -07:00
Howard Mao
0e67d824b4 fix NASTI interconnect bug 2015-09-25 12:12:34 -07:00
Howard Mao
0d763524ef make sure conf address map scales with number of cores 2015-09-25 09:41:19 -07:00
Howard Mao
5e3f9115d3 make sure HTIF mem_mb doesn't exceed MMIOBase 2015-09-25 09:02:35 -07:00
Schuyler Eldridge
f200d0947a Force C++ emulator to always use 1GB for MEM_SIZE 
Fixes #17
 2015-09-24 23:56:41 -04:00
Howard Mao
c20ed350a0 even more Chisel3 compatability changes 2015-09-24 17:55:41 -07:00
Howard Mao
1c0111cc70 uncore merge commit 2015-09-24 17:10:45 -07:00
Howard Mao
8d4d8680bf replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:59:13 -07:00
Howard Mao
4a85c5a510 pull in hardfloat fixes 2015-09-24 16:58:49 -07:00
Scott Beamer
fbc6e695d3 remove bugs from float_fix 2015-09-23 16:11:47 -07:00
Scott Beamer
56daea793a allow float_fix to take stdin (for piping) 2015-09-23 16:09:09 -07:00
Howard Mao
38a9b23ce7 add a flag to only log and dump after a certain number of cycles 2015-09-22 10:32:31 -07:00
Howard Mao
4496e8d4e2 make sure htif_emulator properly sets memory size 2015-09-22 10:32:31 -07:00
Howard Mao
56ecdff52d Implement NASTI-based Mem/IO interconnect 2015-09-22 10:32:31 -07:00
Andrew Waterman
c6bcc832a1 Chisel3: Don't use Vec.fill for IOs 2015-09-20 13:43:56 -07:00
Andrew Waterman
fd58c52250 Update to latest chisel 2015-09-20 13:37:53 -07:00
Colin Schmidt
6f85ed191e Add rocketchip_addons to the list of chisel srcs requiring rebuild 2015-09-16 12:28:03 -07:00
Colin Schmidt
7ecb936bf5 Remove -j from "make run-bmark-tests" in travis 
+currently causes inconsistency in build success
+unclear what root cause is
 2015-09-16 12:27:05 -07:00