Andrew Waterman
e26363a176
Don't pass deprecated -ffaaf option to firrtl ( #1221 )
2018-02-01 14:46:38 -08:00
Jack Koenig
3df401eef7
Bump chisel3 and firrtl and bump sbt to version 1.0.4
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sbt bump must be accompanied by bump to chisel3 and firrtl using sbt
1.0.4
2017-12-18 12:09:21 -08:00
Wesley W. Terpstra
6f3a4cd733
build: pass annotations to firrtl
2017-10-10 23:42:55 -07:00
Andrew Waterman
ea4b1bc349
Use vlsi_mem_gen for verilator flow
2017-08-07 20:36:22 -07:00
Andrew Waterman
21ac28b57a
Don't build verilog twice for emulator and emulator-debug
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Since we aren't using chisel2, the output is the same either way.
2017-08-04 01:02:33 -07:00
Zihao Yu
fc85a3ce02
emulator,Makefile-verilator: add --output-split-cfuncs flag
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* Originally verilator will generate a large cpp file containing a large
function, which costs about 13 min to compile. By using --output-split-cfuncs,
this large function will be splitted into several functions in servral
files. This will greatly improve the compile time with 'make -j'. By '-j32',
the compile time can be reduced to about 1 min.
2017-06-26 14:29:29 +08:00
Wesley W. Terpstra
9eae1fa377
verilator: bump to version 3.904
2017-06-01 10:59:39 -07:00
Schuyler Eldridge
c61714a465
Pass MODEL variable to emulator.cc
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This enables hot-swapping of the top-level test harness by specifying
`MODEL=MyTestHarness` when building the emulator.
2017-03-30 02:08:01 -07:00
Wesley W. Terpstra
93b2fa197e
Artefact output ( #545 )
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* build: stop using empty .prm file
* generator: general-purpose mechanism for creating elaboration artefacts
2017-02-02 19:24:55 -08:00
Henry Cook
c981f8b4f3
More travis job re-balancing ( #481 )
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* [travis] Depend on pre-built docker images rather than travis cache
2016-12-11 22:02:46 -08:00
Henry Cook
9fb7934a37
WIP PR to figure out why travis is failing ( #471 )
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Make travis use a docker image with pre-built toolchain and verilator
2016-12-04 13:10:13 -08:00
Wesley W. Terpstra
3d1a7bd6d3
travis: build verilator and toolchain as part of install
2016-11-21 21:13:26 -08:00
Andrew Waterman
f3c726033a
Make all Chisel invocations depend on FIRRTL_JAR
2016-10-28 11:56:05 -07:00
Andrew Waterman
4f6eb38eeb
Enable Verilator parallel builds
2016-10-04 22:29:39 -07:00
Henry Cook
411ee378de
Provide a GeneratorApp object per user package. Extract RocketTestSuite from coreplex into rocketchip and provide GeneratorApp defaults for other target packages.
2016-09-22 15:59:29 -07:00
Henry Cook
ddcf1b4099
Use PROJECT rather than MODEL in name of binary and generated src files.
2016-09-19 13:23:17 -07:00
Henry Cook
9e2b0aad65
Revert "allow MODEL to be something other than TestHarness"
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This reverts commit bf253aaa97
2016-09-15 11:53:05 -07:00
Howard Mao
bf253aaa97
allow MODEL to be something other than TestHarness
2016-09-14 20:51:56 -07:00
Colin Schmidt
cf3c6fa277
add STOP_COND to emulator & match vsim PRINTF_COND
2016-09-09 11:07:17 -07:00
Howard Mao
08089f695d
allow configuration to be in separate project from test harness
2016-09-01 10:28:07 -07:00
Henry Cook
93c801f598
Streamline the Generator App and associated utilities. Remove deprecated call to chiselMain and useless Chisel2 args. Update arguments to sbt run. ( #227 )
2016-08-25 17:26:28 -07:00
Andrew Waterman
ed827678ac
Write test harness in Chisel
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This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
Howard Mao
dd1fed41b6
generate BootROM contents from assembly code
2016-08-05 16:39:21 -07:00
Andrew Waterman
9751ea0f35
Fix Verilator VCD ( #157 )
2016-07-09 02:37:39 -07:00
Andrew Waterman
32ee5432dd
Fix testing of DefaultSmallConfig; bump rocket et al
2016-07-07 21:23:49 -07:00
Andrew Waterman
f1cbb2ff77
Turn up optimization for Verilator compilation
2016-06-28 14:12:46 -07:00
Andrew Waterman
568bfa6c50
Purge legacy HTIF things
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The SCR file is gone, too, because it was tightly coupled. The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
Howard Mao
daa0f3038f
invoke firrtl jar directly in order to control heap memory usage
2016-06-20 13:02:31 -07:00
Andrew Waterman
4a8e6c773a
Fix +verbose flag for verilator
2016-06-17 21:09:08 -07:00
Palmer Dabbelt
25ade44fe3
Don't build the Verilator man pages ( #141 )
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These failed for Andrew earlier. While it might be paranioa, there's
really no reason to build the man pages so we might as well not bother.
2016-06-16 10:13:21 -07:00
Palmer Dabbelt
1525b4717e
Install Verilator when building the emulator
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We need a fairly new version of Verilator, so I just added a rule to
download and install it on all systems.
2016-06-14 21:21:43 -07:00
Palmer Dabbelt
571b5b2093
Prevent sbt from running multiple times in emulator
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If you have multi-target rules that don't have %s in them, make
interprets that as "run this recipe multiple times, once to produce each
target". If you have %s in the rules, then make interprets it as "run
this recipe once to produce all targets". We want the second one.
2016-06-14 11:59:20 -07:00
Yunsup Lee
3ce8dbb6e5
fix make error mixing implicit and normal rules
2016-06-14 11:59:20 -07:00
Donggyu Kim
99b257316e
replace emulator with verilator for chisel3
2016-06-08 02:43:54 -07:00
