83 lines
3.5 KiB
Plaintext
83 lines
3.5 KiB
Plaintext
#--------------------------------------------------------------------
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# Verilator Generation
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#--------------------------------------------------------------------
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firrtl = $(generated_dir)/$(long_name).fir
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verilog = \
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$(generated_dir)/$(long_name).v \
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$(generated_dir)/$(long_name).behav_srams.v \
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.SECONDARY: $(firrtl) $(verilog)
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$(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
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mkdir -p $(dir $@)
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cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(generated_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
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%.v %.conf: %.fir $(FIRRTL_JAR)
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mkdir -p $(dir $@)
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$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $*.v -X verilog --infer-rw $(MODEL) --repl-seq-mem -c:$(MODEL):-o:$*.conf
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$(generated_dir)/$(long_name).behav_srams.v : $(generated_dir)/$(long_name).conf $(VLSI_MEM_GEN)
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cd $(generated_dir) && \
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$(VLSI_MEM_GEN) $(generated_dir)/$(long_name).conf > $@.tmp && \
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mv -f $@.tmp $@
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# Build and install our own Verilator, to work around versionining issues.
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VERILATOR_VERSION=3.904
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VERILATOR_SRCDIR ?= verilator/src/verilator-$(VERILATOR_VERSION)
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VERILATOR_TARGET := $(abspath verilator/install/bin/verilator)
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INSTALLED_VERILATOR ?= $(VERILATOR_TARGET)
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$(VERILATOR_TARGET): $(VERILATOR_SRCDIR)/bin/verilator
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$(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata
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touch $@
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$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile
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$(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin
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touch $@
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$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure
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mkdir -p $(dir $@)
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cd $(dir $@) && ./configure --prefix=$(abspath verilator/install)
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$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz
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rm -rf $(dir $@)
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mkdir -p $(dir $@)
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cat $^ | tar -xz --strip-components=1 -C $(dir $@)
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touch $@
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verilator/verilator-$(VERILATOR_VERSION).tar.gz:
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mkdir -p $(dir $@)
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wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
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verilator: $(INSTALLED_VERILATOR)
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# Run Verilator to produce a fast binary to emulate this circuit.
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VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
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VERILATOR_FLAGS := --top-module $(MODEL) \
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+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
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--output-split 20000 \
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--output-split-cfuncs 20000 \
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-Wno-STMTDLY --x-assign unique \
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-I$(base_dir)/vsrc \
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-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -DTEST_HARNESS=V$(MODEL) -include $(base_dir)/csrc/verilator.h"
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cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
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headers = $(wildcard $(base_dir)/csrc/*.h)
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model_header = $(generated_dir)/$(long_name)/V$(MODEL).h
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model_header_debug = $(generated_dir_debug)/$(long_name)/V$(MODEL).h
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$(emu): $(verilog) $(cppfiles) $(headers) $(INSTALLED_VERILATOR)
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mkdir -p $(generated_dir)/$(long_name)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(long_name) \
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-o $(abspath $(sim_dir))/$@ $(verilog) $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "-I$(generated_dir) -include $(model_header)"
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$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir)/$(long_name) -f V$(MODEL).mk
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$(emu_debug): $(verilog) $(cppfiles) $(headers) $(generated_dir)/$(long_name).d $(INSTALLED_VERILATOR)
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mkdir -p $(generated_dir_debug)/$(long_name)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(long_name) --trace \
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-o $(abspath $(sim_dir))/$@ $(verilog) $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug)"
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$(MAKE) VM_PARALLEL_BUILDS=1 -C $(generated_dir_debug)/$(long_name) -f V$(MODEL).mk
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