1
0
rocket-chip/emulator/Makefrag-verilator

81 lines
4.0 KiB
Plaintext

#--------------------------------------------------------------------
# Verilator Generation
#--------------------------------------------------------------------
firrtl = $(generated_dir)/$(MODEL).$(CONFIG).fir
firrtl_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
verilog = $(generated_dir)/$(MODEL).$(CONFIG).v
verilog_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).v
.SECONDARY: $(firrtl) $(firrtl_debug) $(verilog) $(verilog_debug)
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).prm $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir)"
mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
$(generated_dir_debug)/%.$(CONFIG).fir $(generated_dir_debug)/%.$(CONFIG).prm $(generated_dir_debug)/%.$(CONFIG).d: $(chisel_srcs)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(MODEL) $(CONFIG) --targetDir $(generated_dir_debug)"
mv $(generated_dir_debug)/$(MODEL).fir $(generated_dir_debug)/$(MODEL).$(CONFIG).fir
%.v: %.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog
# Build and install our own Verilator, to work around versionining issues.
VERILATOR_VERSION=3.884
VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION)
INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator)
$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator
$(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata
touch $@
$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile
$(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin
touch $@
$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure
mkdir -p $(dir $@)
cd $(dir $@) && ./configure --prefix=$(abspath verilator/install)
$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz
rm -rf $(dir $@)
mkdir -p $(dir $@)
cat $^ | tar -xz --strip-components=1 -C $(dir $@)
touch $@
verilator/verilator-$(VERILATOR_VERSION).tar.gz:
mkdir -p $(dir $@)
wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
# Run Verilator to produce a fast binary to emulate this circuit.
VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
VERILATOR_FLAGS := --top-module $(MODEL) +define+PRINTF_COND=\$$c\(\"verbose\"\) --assert \
-Wno-UNSIGNED -Wno-COMBDLY -Wno-MULTIDRIVEN -Wno-WIDTH -Wno-STMTDLY -Wno-SELRANGE -Wno-IMPLICIT \
-CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h"
cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
model_header = $(generated_dir)/$(MODEL).$(CONFIG)/V$(MODEL).h
model_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG)/V$(MODEL).h
$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(consts_header)
$(CXX) $(CXXFLAGS) -DVERILATOR -I$(generated_dir) -c -o $@ $<
$(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(consts_header_debug)
$(CXX) $(CXXFLAGS) -DVERILATOR -I$(generated_dir_debug) -c -o $@ $<
$(emu): $(verilog) $(cppfiles) libdramsim.a $(consts_header) $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir)/$(MODEL).$(CONFIG)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header) -include $(scr_header)"
$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
$(emu_debug): $(verilog_debug) $(cppfiles) libdramsim.a $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR)
mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG) --trace \
-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug) -include $(scr_header_debug)"
$(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk