Henry Cook
6cff1c13d8
Refer to traits moved to uncore, add UncoreConfiguration to top
2012-10-16 14:22:23 -07:00
Andrew Waterman
b9a2af697d
turn off HAVE_VEC as it's currently broken
...
the new I$/frontend needs to be integrated
2012-10-16 07:38:19 -07:00
Andrew Waterman
0a640f2cc6
make DecodeLogic deterministic (hopefully)
2012-10-16 04:51:21 -07:00
Andrew Waterman
5821900329
don't refetch from I$ if on same 16B block
2012-10-16 02:24:38 -07:00
Andrew Waterman
b955985b38
improve divider QoR
2012-10-16 02:24:38 -07:00
Andrew Waterman
197154c485
use BTB for JALR
2012-10-16 02:24:37 -07:00
Andrew Waterman
fc648d13a1
remove old Mux1H; add implicit conversions
2012-10-16 02:24:37 -07:00
Andrew Waterman
661f8e635b
merge I$, ITLB, BTB into Frontend
2012-10-16 02:24:37 -07:00
Andrew Waterman
fcd69dba98
add optional early-out to mul/div
2012-10-16 02:24:37 -07:00
Andrew Waterman
27ddff1adb
simplify and improve multiplier
2012-10-16 02:24:37 -07:00
Henry Cook
8970b635b2
improvements to implicit RocketConfiguration parameter
2012-10-15 16:29:49 -07:00
Henry Cook
a7a4e65690
Initial verison of reading config from files
2012-10-15 16:05:50 -07:00
Henry Cook
5d2a470215
all rocket-specific arbiters in one file and refactored traits slightly
2012-10-15 16:05:32 -07:00
Huy Vo
1864e41361
memserdes + slowio out of rocket and into uncore
2012-10-10 15:25:24 -07:00
Huy Vo
fe21142972
fixed memdessert unpacking
2012-10-09 13:03:17 -07:00
Henry Cook
9025d0610c
first pass at configuration object passed as implicit parameter
2012-10-07 22:37:29 -07:00
Henry Cook
dfdfddebe8
constants as traits
2012-10-07 22:20:03 -07:00
Henry Cook
b5ff436092
decode constant object split into multiple objects
2012-10-05 15:50:42 -07:00
Andrew Waterman
ed8cc4a1cf
eliminate D$ probe->WB critical path
2012-10-04 09:05:14 -07:00
Huy Vo
e909093f37
factoring out uncore into separate uncore repo
2012-10-01 16:08:41 -07:00
Henry Cook
b9a9664de5
uncore and rocket changes for new xact types
2012-10-01 10:47:36 -07:00
Huy Vo
d9cb96c0ae
factored out common stuff to ChiselUtil
2012-09-27 22:53:34 -07:00
Andrew Waterman
667b4ee858
remove Queue flush port (override reset instead)
2012-08-22 13:39:19 -07:00
Andrew Waterman
d4a001b867
add PriorityMux; use to implement PriorityEncoder
2012-08-22 13:38:25 -07:00
Andrew Waterman
743e032f06
generalize interface to DecodeLogic
2012-08-22 13:38:07 -07:00
Andrew Waterman
0f20771664
rename queue to Queue
...
fixes build with case-insensitive file system
2012-08-08 22:11:59 -07:00
Andrew Waterman
897a4e349b
fix some LLC control bugs
2012-08-06 17:10:04 -07:00
Andrew Waterman
e9c35b4923
ameliorate DTLB kill->rdy critical path
2012-08-06 17:05:05 -07:00
Andrew Waterman
b94e6915ab
refactor IPIs; use new tohost/fromhost protocol
2012-08-03 19:00:34 -07:00
Andrew Waterman
6510f020c7
fix deadlock in coherence hub
2012-08-03 19:00:03 -07:00
Andrew Waterman
e3726c4db0
fix control bug in LLC
...
structural hazard on tag ram caused deadlock
2012-08-03 18:59:37 -07:00
Andrew Waterman
def913096e
pipeline LLC further
2012-07-31 17:45:14 -07:00
Andrew Waterman
3a8f3e0de5
further pipeline the LLC
2012-07-30 20:12:11 -07:00
Andrew Waterman
80c243469e
add flow queues and skid buffers
...
hopefully they work
2012-07-30 18:47:12 -07:00
Andrew Waterman
be4fa936dd
fix PriorityEncoderOH bug
2012-07-30 18:28:54 -07:00
Andrew Waterman
2ec76390e3
improve PriorityEncoderOH and add Counter util
2012-07-30 16:06:55 -07:00
Yunsup Lee
2af84f994a
remove reset pin on llc
2012-07-28 21:14:51 -07:00
Yunsup Lee
0a1cd1175c
add reset pin to llc
2012-07-27 18:44:39 -07:00
Huy Vo
db91c4cf6c
hwacha
2012-07-27 18:13:20 -07:00
Huy Vo
32a16d183f
consts file doesn't depend on WIDTH_PVFB if HAVE_PVFB == false
2012-07-27 18:13:20 -07:00
Andrew Waterman
130fa95ed6
expand HTIF's PCR register space
2012-07-27 14:52:39 -07:00
Andrew Waterman
7778802395
reduce number of outstanding transactions
2012-07-26 14:51:41 -07:00
Andrew Waterman
9c50621a19
remove chip-specific uncore gunk
2012-07-26 03:26:52 -07:00
Andrew Waterman
a5bea4364f
memory system bug fixes
2012-07-26 00:05:21 -07:00
Yunsup Lee
3a2b305ddf
change htif width to 16
2012-07-25 17:25:50 -07:00
Andrew Waterman
177dbdadd9
merge HTIF port and backup memory port
2012-07-25 00:18:02 -07:00
Yunsup Lee
309193dd07
change llc size
2012-07-24 14:10:29 -07:00
Yunsup Lee
6541cf22a4
fix bug in coherence hub, respect xact_rep.ready
2012-07-23 20:56:55 -07:00
Yunsup Lee
f4e3e72ad1
hoist HTIF_WIDTH out to consts
2012-07-23 17:30:04 -07:00
Andrew Waterman
a21c355114
fix htif split request/response
2012-07-23 17:15:16 -07:00
Andrew Waterman
938effc053
don't dequeue probe queue during reset
2012-07-22 21:05:52 -07:00
Yunsup Lee
379f021359
change ioHTIF interface between the tile/uncore boundary to cope with asynchrony
2012-07-22 18:26:02 -07:00
Yunsup Lee
c892950bf1
hoist out uncore as its own component
2012-07-22 17:48:17 -07:00
Huy Vo
0a97d6ab4d
type casting
2012-07-18 13:03:35 -07:00
Andrew Waterman
f42c6afed2
decouple all interfaces between tile and top
...
also, add an "incoherent" bit to tilelink to indicate no probes needed
2012-07-17 22:55:40 -07:00
Andrew Waterman
4e44ed7400
allow back pressure on IPI requests
2012-07-17 22:55:40 -07:00
Yunsup Lee
f633a55722
fix dcache tag array size
2012-07-16 22:19:03 -07:00
Andrew Waterman
e496cd7584
use Mem to implement queues to speed things up
2012-07-13 21:48:05 -07:00
Huy Vo
fd95159837
INPUT/OUTPUT orderring swapped
2012-07-12 18:16:57 -07:00
Andrew Waterman
bac82762d3
use only one (wide) tag ram for set assoc. caches
2012-07-12 14:50:12 -07:00
Andrew Waterman
429fcbed8e
fix some LLC bugs
2012-07-11 17:56:39 -07:00
Andrew Waterman
f645fb4dd7
add L2$
...
It still has performance bugs but no correctness bugs AFAIK.
2012-07-10 05:23:29 -07:00
Andrew Waterman
5035374f36
update to new chisel
2012-07-08 17:59:41 -07:00
Andrew Waterman
39d198ecdc
fix htif handling of large memory reads
2012-06-26 19:12:11 -07:00
Andrew Waterman
4e5f874266
update to new chisel/hwacha
2012-06-08 00:13:14 -07:00
Huy Vo
a99cebb483
ioDecoupled -> FIFOIO, ioPipe -> PipeIO
2012-06-06 18:22:56 -07:00
Huy Vo
04304fe788
moving util out into Chisel standard library
2012-06-06 12:51:26 -07:00
Huy Vo
c975c21e44
views removed
2012-06-06 12:51:26 -07:00
Andrew Waterman
943b6d0616
remove debug println
2012-06-06 02:48:48 -07:00
Andrew Waterman
7f6319047e
update to new scala/chisel/Mem
2012-06-06 02:47:22 -07:00
Huy Vo
7408c9ab69
removing wires
2012-05-24 10:42:39 -07:00
Huy Vo
181b20d69c
working vec unit with pvfb
2012-05-24 10:38:14 -07:00
Andrew Waterman
faee45bf4c
fix setpcr/clearpcr not writing rd
2012-05-21 07:25:35 -07:00
Yunsup Lee
c9602a0d2e
fix vector control decode bug
2012-05-15 10:26:37 -07:00
Gage W Eads
d0bc995c88
Fixed IRQ_IPI -> IRQ_TIMER typo
2012-05-14 22:25:12 -07:00
Andrew Waterman
a2f6d01c1b
add programmable coreid register
2012-05-09 03:09:22 -07:00
Andrew Waterman
e0e1cd5d32
add IPIs and an IPI test
...
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
2012-05-08 22:58:00 -07:00
Henry Cook
87cbae2c8a
Removed defunct ioDmem
2012-05-07 17:31:39 -07:00
Andrew Waterman
b851f1b34c
support maximum-MTU HTIF packets
2012-05-03 21:11:43 -07:00
Andrew Waterman
171c87002e
reduce HTIF clock divider for now
2012-05-03 04:21:11 -07:00
Andrew Waterman
e1f9dc2c1f
generalize page table walker
...
also, don't instantiate vitlb when !HAVE_VEC
2012-05-03 02:29:09 -07:00
Andrew Waterman
2d4e5d3813
fix pseudo-LRU verilog generation bug
2012-05-02 19:31:31 -07:00
Henry Cook
622a801bb1
Refactored cpu/cache interface to use nested bundles
2012-05-02 11:54:28 -07:00
Andrew Waterman
65ff397122
improved instruction decoding
...
it now makes use of don't-cares by performing logic minimization
2012-05-01 20:16:36 -07:00
Andrew Waterman
4cfa6cd9a8
force Top.main's return type to Unit
2012-05-01 19:55:16 -07:00
Andrew Waterman
5819beed64
use parameterized FP units
2012-05-01 01:25:43 -07:00
Andrew Waterman
eafdffe125
simplify page table walker; speed up emulator
2012-05-01 01:24:36 -07:00
Andrew Waterman
c13d3e6f88
fix probe tag read-modify-write atomicity violation
2012-04-26 02:29:31 -07:00
Andrew Waterman
66f86a2194
use pseudo-LRU replacement for TLBs
2012-04-26 02:29:30 -07:00
Andrew Waterman
a0378c5d2f
remove faulting TLB entry after page fault
...
this vastly reduces the frequency with which the TLB must be flushed
2012-04-26 02:29:30 -07:00
Andrew Waterman
6d8fc74378
fix DTLB permissions bug
2012-04-26 02:29:30 -07:00
Henry Cook
1ed89f1cab
Fixed abort bug: removed uneeded state, added mshr guard on xact_abort.valid and xact_init.ready on same cycle
2012-04-24 17:17:42 -07:00
Henry Cook
55e86b5cf4
Fixed coherence bug: probe counting for single tile
2012-04-24 17:17:13 -07:00
Henry Cook
a39080d0b1
Fixed abort bug: xact_abort.ready was not pinned high
2012-04-24 17:16:40 -07:00
Andrew Waterman
fb4408b150
fix AMO replay/coherence deadlock
2012-04-15 22:56:02 -07:00
Andrew Waterman
724735f13f
fix writeback bug
2012-04-13 03:16:48 -07:00
Andrew Waterman
00d934cfac
fix coherence bugs in cache
2012-04-12 21:57:37 -07:00
Henry Cook
fef58f1b3a
Policy determined by constants. MSI policy added.
2012-04-11 17:56:59 -07:00
Andrew Waterman
c0ec3794bf
coherence mostly works now
2012-04-10 02:22:45 -07:00
Henry Cook
3cdd166153
Refactored coherence as member rather than trait. MI and MEI protocols.
2012-04-10 00:09:58 -07:00
Henry Cook
9c8f849f50
defined abstract coherence traits in base trait, added Incoherent trait, cleaned up incoherent policy
2012-04-09 23:29:32 -07:00
Henry Cook
551e09c9d5
changed coherence type width names to represent max sizes for all protocols
2012-04-09 23:29:32 -07:00
Henry Cook
0b4937f70f
changed coherence message type names
2012-04-09 23:29:31 -07:00
Henry Cook
ed79ec98f7
Refactored coherence better from uncore hub, better coherence function names
2012-04-09 23:29:31 -07:00
Andrew Waterman
aee9378712
fix coherence bug with multiple probe replies
2012-04-09 21:40:35 -07:00
Huy Vo
c9c3bd02bc
kill mem stage if fpu nacks in mem stage
2012-04-01 17:02:32 -07:00
Andrew Waterman
7f254d9670
refine FP bugfixes
2012-04-01 14:52:33 -07:00
Huy Vo
c7c35322c2
two bug fixes to fpu
2012-03-31 22:23:51 -07:00
Andrew Waterman
a09e8d1c55
remove I$ prefetcher for now
...
there's a bug in it, and I don't have time to fix it at the moment.
2012-03-27 15:43:56 -07:00
Andrew Waterman
452876af37
fence on vvcfg; implement fence.v.g correctly
2012-03-27 14:49:00 -07:00
Yunsup Lee
bb704dc0c9
fix vector length calc bug, thanks chris and andrew
2012-03-27 12:04:07 -07:00
Andrew Waterman
6bda8674bd
no dessert tonight :(
2012-03-26 23:50:09 -07:00
Yunsup Lee
a70f0414fa
fix a workaroundable bug
2012-03-26 20:51:54 -07:00
Yunsup Lee
32d95e9594
fix -1:0 index problem for direct map case
2012-03-26 17:00:01 -07:00
Andrew Waterman
e2fe525fb6
remove bug from dessert
2012-03-26 14:18:57 -07:00
Yunsup Lee
e6b0e565de
turn HAVE_VEC on
2012-03-26 01:21:39 -07:00
Andrew Waterman
5f53cd4ac1
reduce HTIF width
2012-03-25 23:49:59 -07:00
Andrew Waterman
ef505de017
reduce HTIF width
2012-03-25 23:49:45 -07:00
Andrew Waterman
31f0b600fd
add dessert
2012-03-25 23:03:20 -07:00
Andrew Waterman
1666d3fbd7
loop host.in to host.out during reset
2012-03-25 21:45:10 -07:00
Andrew Waterman
f62a02ab54
remove dumb stuff in top.scala
2012-03-25 21:30:01 -07:00
Andrew Waterman
88bf8a4f23
add mem serdes unit
2012-03-25 17:03:58 -07:00
Andrew Waterman
7fa93da4f5
add backup memory port (disabled for now)
2012-03-25 15:49:32 -07:00
Yunsup Lee
1f33f6bb58
HAVE_VEC is on
2012-03-24 20:54:43 -07:00
Andrew Waterman
86d56ff67b
refactor cpu/i$/d$ into Tile (rather than Top)
2012-03-24 16:57:28 -07:00
Andrew Waterman
3a487ac89b
improve htif<->pcr interface
2012-03-24 16:57:28 -07:00
Andrew Waterman
54fa6f660d
new supervisor mode
2012-03-24 13:03:31 -07:00
Yunsup Lee
65929a62e3
fix reset value for appvl
2012-03-22 15:32:04 -07:00
Yunsup Lee
aaed0241af
get rid of vxcptwait
2012-03-21 15:09:04 -07:00
Yunsup Lee
023734175d
now fence stalls in decode
2012-03-20 17:10:05 -07:00
Yunsup Lee
e450e3aa40
fix irt counter bug regarding vector stuff
2012-03-20 17:09:54 -07:00
Yunsup Lee
7d7d7f49f9
change the tlb arbiter to a round robing one
2012-03-20 15:21:36 -07:00
Yunsup Lee
1cddd5de56
fix amo locking up problem
2012-03-20 02:16:28 -07:00
Yunsup Lee
56cb9b7a63
fix bug in coherence hub, specifically in abort handling logic
2012-03-20 02:16:28 -07:00
Yunsup Lee
c036fff79c
fix id interrupt signal
2012-03-19 15:13:57 -07:00
Yunsup Lee
0edea00166
now HAVE_VEC is true, since it passes the emulator
2012-03-19 03:10:00 -07:00
Yunsup Lee
264732556f
fixes to match verilog X semantics
2012-03-19 03:10:00 -07:00
Andrew Waterman
bd27d0fab2
can now take interrupts on stalled instructions
2012-03-19 01:02:06 -07:00
Andrew Waterman
2ed0be65f9
fix RRArbiter
2012-03-19 00:19:33 -07:00
Yunsup Lee
ba06cd953e
add chosen
2012-03-18 20:43:17 -07:00
Andrew Waterman
c4a91303fb
update vector fence names and encoding
2012-03-18 20:42:38 -07:00
Yunsup Lee
2a01f558ba
fix unmasked valid bug in ctrl_vec
2012-03-18 19:55:24 -07:00
Yunsup Lee
98e10ddc3c
update vector exception instructions
2012-03-18 16:36:12 -07:00
Yunsup Lee
7493d55d3f
add pf fault handling
2012-03-18 15:06:39 -07:00
Yunsup Lee
62ada5ea9e
hookup vitlb ptw port
2012-03-17 23:01:06 -07:00
Yunsup Lee
b793d63182
no vector interrupt masking
2012-03-17 23:01:06 -07:00
Yunsup Lee
8a4f95e617
changes to xcpt handling
2012-03-17 17:50:37 -07:00
Yunsup Lee
8c50c81b81
drop vec_irq_aux pcr register, now everything goes through badvaddr
2012-03-17 14:03:57 -07:00
Yunsup Lee
3b4680a834
add vitlb exception port
2012-03-17 14:03:33 -07:00
Andrew Waterman
a47eeb9571
retime D$ bypass into beginning of EX stage
2012-03-16 18:35:54 -07:00
Andrew Waterman
6c26921766
reduce D$ critical path through page table walker
...
costs an extra cycle per page table level to resolve a TLB miss. too bad.
2012-03-16 18:35:54 -07:00
Yunsup Lee
d38603a4ee
change number of tlb entries
2012-03-16 17:08:03 -07:00
Andrew Waterman
f0157b9e2a
fix coherence bug
...
popping wrong store dependence queue
2012-03-16 01:24:07 -07:00
Andrew Waterman
cfca2d1411
clean up cache interfaces; avoid reserved keywords
2012-03-16 00:44:16 -07:00
Andrew Waterman
820884c7e6
fix probes for smaller cache sizes
...
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
2012-03-15 23:08:30 -07:00
Andrew Waterman
4684171ac6
fix fence.i for associative caches
2012-03-15 21:23:21 -07:00
Andrew Waterman
2b0bc8df2b
use divided clk for htif. UDPATE YOUR FESVR
...
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
2012-03-15 18:36:51 -07:00
Yunsup Lee
ba566f246e
change icache parameters
2012-03-15 15:35:12 -07:00
Yunsup Lee
72006160dc
fix vxcptwait inst bug, it was incorrect when exception_valid was on before do_xcptwait
2012-03-15 02:10:21 -07:00
Yunsup Lee
f972977da1
refactored VMU, now uses one skid buffer
2012-03-15 01:10:17 -07:00
Henry Cook
b5fa86e844
4-way associative by default
2012-03-14 17:51:12 -07:00
Andrew Waterman
7dde7099d2
use broadcast hub and coherent HTIF
2012-03-14 16:44:35 -07:00
Yunsup Lee
b19d783fbd
add vector irq handler
2012-03-14 14:15:28 -07:00
Yunsup Lee
040d62f372
refactored vector exception handling interface
2012-03-13 23:45:34 -07:00
Yunsup Lee
b100544b25
datapath to read out vector state
2012-03-13 23:45:34 -07:00
Yunsup Lee
5655dbd5da
add vvcfg and vtcfg instructions
2012-03-13 23:45:34 -07:00
Andrew Waterman
ab6c9350db
fix minor coherence bugs
2012-03-13 19:10:54 -07:00
Andrew Waterman
1788c34113
parameterize broadcast hub by # of tiles
2012-03-13 17:12:01 -07:00
Andrew Waterman
1492457df5
add probe replies to HTIF
2012-03-13 16:56:47 -07:00
Andrew Waterman
b0f798962c
add probe unit
2012-03-13 16:43:51 -07:00
Huy Vo
fdffb124e3
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-03-13 12:34:39 -07:00
Huy Vo
6fd1527476
fix to rocket vec_dpath, updating makefiles to run xcpt test cases
2012-03-13 12:34:02 -07:00
Henry Cook
287bc1c262
Further refinement of tag_match/tag_hit signals
2012-03-13 11:48:12 -07:00
Andrew Waterman
d76b05bde1
fix way selection on D$ write upgrades
2012-03-13 02:21:02 -07:00
Andrew Waterman
fd29e00db0
support non-power-of-2 queue sizes
...
need to manually wrap queue pointers.
2012-03-13 01:58:28 -07:00
Henry Cook
cbf7b13341
fix hit logic for amos
2012-03-12 22:01:52 -07:00
Henry Cook
6229a33dc4
fixed cache controller flush unit deadlock
2012-03-12 22:01:52 -07:00
Henry Cook
ea0775643b
fixed abort bug
2012-03-12 22:01:52 -07:00
Yunsup Lee
1ba5e7b865
changes to the vector exception interface
2012-03-11 21:38:47 -07:00
Yunsup Lee
113a94a21d
add vector hold waits
2012-03-11 16:29:19 -07:00
Yunsup Lee
e42a4c767e
don't stall on vector fences, keep replaying
2012-03-11 16:29:19 -07:00
Henry Cook
c5dd37ae80
bugfix in locking arbiter
2012-03-11 15:47:27 -07:00
Henry Cook
4ebf637642
More broadcast hub bugfixes
2012-03-11 14:17:27 -07:00
Henry Cook
a4d0025187
fix icache prefetch global_xact_id bug
2012-03-11 00:50:11 -08:00
Yunsup Lee
1aa4b0e93d
going back to null coherence hub
2012-03-10 20:16:20 -08:00
Andrew Waterman
8ffdac9526
fix D$ store-upgrade bug
...
loads to the same address as stores that cause an upgrade
could return the old value
2012-03-10 15:50:10 -08:00
Andrew Waterman
4f4b990a4f
fix null hub store ack bug
2012-03-10 15:19:12 -08:00
Yunsup Lee
44ff22a26f
vector exception handler now handles prefetches correctly
2012-03-10 12:54:36 -08:00
Andrew Waterman
7eb73c325e
fix signedness of zero fmul results
...
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0. Now we
add -0.0 if rs1*rs2 is negative.
2012-03-10 00:21:51 -08:00
Andrew Waterman
e3a68848e0
fix D$ critical paths and fix verilog build
2012-03-09 20:02:51 -08:00
Henry Cook
e591d83e91
Fixed global_xact_id propagation bug
2012-03-09 11:05:44 -08:00
Henry Cook
9319130483
Special cased NTILES == 1 due to log2up revision
2012-03-09 11:04:58 -08:00
Andrew Waterman
85504f0ddc
fix bug in fence.i and improve test
2012-03-09 03:26:05 -08:00
Andrew Waterman
766bac88f8
refactor D$ writebacks and flushes
...
MSHRs now arbitrate for writebacks and handle flushes.
2012-03-09 02:55:46 -08:00
Andrew Waterman
ff2e47f380
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-03-09 02:08:55 -08:00
Yunsup Lee
a1b30282dd
major refactoring on vector exception interface
2012-03-09 01:09:22 -08:00
Yunsup Lee
8acbe98f53
change how fence.*.cv works, now control processor stalls on the fence instruction
2012-03-08 23:32:31 -08:00
Henry Cook
22726ae646
icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data
2012-03-08 18:47:32 -08:00
Henry Cook
4d2e7172f6
Added require_ack field to TransactionReply bundle
2012-03-08 18:07:44 -08:00
Henry Cook
35c4bd4084
Hub addr comparison bug fix
2012-03-08 16:39:05 -08:00
Henry Cook
788ad327da
Fixed dependency queue bug in Broadcast Hub
2012-03-08 11:36:10 -08:00
Henry Cook
7f43dee0c9
PriorityEncoder apply() no longer has recursive depth param
2012-03-08 01:04:26 -08:00
Andrew Waterman
5a7c5772a8
clearly distinguish PPN and cache tag
2012-03-07 23:11:17 -08:00
Andrew Waterman
941873bad1
coherence hub fixes
2012-03-07 21:03:44 -08:00
Henry Cook
7deff5fbe2
Broadcast hub bug fixes for load uncached mem req and store uncached xact rep
2012-03-07 11:40:49 -08:00
Andrew Waterman
c09eeb7fd2
fix D$ next-state logic
...
it was using the CPU command from the wrong pipeline stage,
which was a don't-care with ThreeStateIncoherence.
2012-03-07 01:42:08 -08:00
Andrew Waterman
a0c9452b86
change D$ to use FourStateCoherence protocol
...
instead of ThreeStateIncoherence.
2012-03-07 01:26:35 -08:00
Andrew Waterman
6e2610b0ad
fix Mux1H for bundles
2012-03-06 23:38:36 -08:00
Yunsup Lee
81dcb194d3
new vector exception interface
2012-03-06 22:39:15 -08:00
Henry Cook
47a2097507
unified coherence trait functions
2012-03-06 17:33:11 -08:00
Henry Cook
3dd404dcf4
hub code cleanup
2012-03-06 17:01:47 -08:00
Henry Cook
c0ed010bc9
newTransactionOnMiss()
2012-03-06 15:54:41 -08:00
Henry Cook
962e5a54af
Added store dependency queues to BroadcastHub. Minor improvements to utils.
2012-03-06 15:54:41 -08:00
Andrew Waterman
499c5b4a2e
automatically infer MEM_TAG_BITS
2012-03-06 15:49:28 -08:00
Andrew Waterman
6e16b04ada
implement transaction finish messages
2012-03-06 15:48:08 -08:00
Yunsup Lee
dba99e07a9
set MEM_TAG_BITS to 5 when HAVE_VEC is true, since NMSHR=4
2012-03-06 08:54:21 -08:00
Andrew Waterman
5f33ab24b0
fix merge conflict
...
oops :(
2012-03-06 02:02:53 -08:00
Andrew Waterman
5f12990dfb
support memory transaction aborts
2012-03-06 00:35:02 -08:00
Henry Cook
950b5cd900
Added aborted data dequeueing state machine for BroadcastHub
2012-03-05 17:44:30 -08:00
Henry Cook
5c66a6699c
Broadcast hub control logic bugfixes and code cleanup
2012-03-05 17:27:55 -08:00
Yunsup Lee
a950d526d2
add prefetch count queue
2012-03-05 12:09:41 -08:00
Yunsup Lee
d4ec7ff4d9
refined vector exception interface
2012-03-03 16:11:54 -08:00
Yunsup Lee
e28a551368
refactor code related to vector exceptions
...
- revisied interfaces
- new instructions
2012-03-03 15:15:00 -08:00
Yunsup Lee
f9fb3978ca
fix store prefetch bug, it no longer occupies an entry in the sdq
2012-03-03 15:14:59 -08:00
Henry Cook
1b3307df32
Removed has_data fields from all coherence messages, increased message type names to compensate
2012-03-02 23:51:53 -08:00
Henry Cook
35f97bf858
Filled out 4 state coherence functions for cache
2012-03-02 21:58:50 -08:00
Henry Cook
00989c58bd
Correction to probe reply w/ data handling
2012-03-02 17:20:22 -08:00
Andrew Waterman
1e1926ce63
flip direction of ioPipe to match ioDecoupled
2012-03-02 16:18:32 -08:00
Henry Cook
7406908d4a
BroadcastHub can be elaborated by C and vlsi backends
2012-03-02 12:19:27 -08:00
Yunsup Lee
54baa0713c
hack fence.g.cv to support waiting the control processor
2012-03-02 02:10:26 -08:00
Yunsup Lee
1054cec087
add vec countq interface
2012-03-02 00:43:32 -08:00
Yunsup Lee
8678b3d70c
clean up ioDecoupled/ioPipe interface
2012-03-01 20:48:46 -08:00
Andrew Waterman
6d03d75835
improve D$ internal interfaces
2012-03-01 20:20:15 -08:00
Andrew Waterman
28cacd953f
D$ cleanup - merge ReplayUnit and MSHRFile
2012-03-01 19:30:56 -08:00
Andrew Waterman
52101373e0
clean up D$ store data unit
2012-03-01 19:20:00 -08:00
Henry Cook
da39810bb2
Fixed elaboration errors in LockingArbiter and BoradcastHub. Fixed ioDecoupled direction error in XactTracker
2012-03-01 18:24:22 -08:00
Henry Cook
9d7707a0a2
Made xact_rep an ioValid, removed has_data member
2012-03-01 18:24:21 -08:00
Yunsup Lee
c7b01230f4
fix mul/div when waddr=0, can't believe torture didn't find this one
2012-03-01 10:15:27 -08:00
Henry Cook
c6162ac743
Unified hub ios. Fixed some hub elaboration errors.
2012-03-01 01:20:57 -08:00
Yunsup Lee
a8ef5e9e27
change NMSHR when HAVE_VEC is true
2012-03-01 01:07:47 -08:00
Yunsup Lee
6847160343
refactor arbiter priorities
2012-03-01 00:22:34 -08:00
Yunsup Lee
f641b44fb8
changes after the module uniquify bug fix
2012-02-29 22:00:59 -08:00
Henry Cook
813ffcbf3e
Finished broadcast hub with split mem req types. Untested.
2012-02-29 17:58:15 -08:00
Yunsup Lee
4939b72ba5
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-29 17:12:02 -08:00
Yunsup Lee
20d0088f66
temporary fix to match bit widths for Mem
2012-02-29 17:09:31 -08:00
Henry Cook
008ad1f45b
Added 'locking' arbiter that won't rearbitrate until the lock signal on the current winning input is low
2012-02-29 17:05:06 -08:00
Henry Cook
c723ef4c50
ioDecoupled now allows inner bundle to be used in covariant positions, i.e. it accepts subtypes
2012-02-29 16:46:16 -08:00
Andrew Waterman
c38065d0e8
clean up priority encoders
2012-02-29 16:13:14 -08:00
Andrew Waterman
b9ec69f8f5
add new Queue singleton
2012-02-29 14:21:42 -08:00
Andrew Waterman
012da6002e
replace tile memory interface with ioTileLink
...
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
2012-02-29 03:10:47 -08:00
Henry Cook
082b38d315
Broadcast hub nears completion. Still does not handle generation/arbitration for decoupled mem reqs.
2012-02-29 02:59:27 -08:00
Henry Cook
8ff6e21e3a
Fixed race between read resps/reps and write req/reps in null hub
2012-02-29 00:44:03 -08:00
Andrew Waterman
c99f6bbeb7
separate memory request command and data
...
also, merge some VLSI/C++ test harness functionality
2012-02-28 19:06:23 -08:00
Henry Cook
040aa9fe02
Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem
2012-02-28 17:33:32 -08:00
Daiwei Li
3f998b1353
send vcfg and setvl to vu prefetch queues
2012-02-28 14:54:48 -08:00
Henry Cook
5cc10337b4
Null coherence hub. Begin work on internal tracker logic
2012-02-27 19:10:15 -08:00
Andrew Waterman
2b1c07c723
replace ioDCache with ioMem
2012-02-27 18:36:09 -08:00
Andrew Waterman
1d41a41afa
remove extraneous constants
2012-02-27 17:49:48 -08:00
Yunsup Lee
3d96a2d4f0
add fpu.dec.wen := false when HAVE_FPU is turned off
2012-02-27 14:00:58 -08:00
Henry Cook
f0588a0052
Added probe_req ready sigs, GenArray to Vec
2012-02-27 11:26:18 -08:00
Henry Cook
7a8f53a117
probe req transactors in coherence hub
2012-02-27 09:24:33 -08:00
Henry Cook
2275239f33
xact init transactors in coherence hub
2012-02-27 09:24:32 -08:00
Yunsup Lee
bfd0ae125e
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
2012-02-26 23:46:51 -08:00
Andrew Waterman
6e706c7c74
fix yet another AMO-related replay bug
2012-02-26 20:20:45 -08:00
Andrew Waterman
e12b9eae93
remove ext_mem interface
...
hindsight is 20/20
2012-02-26 18:53:39 -08:00
Andrew Waterman
2d04664a98
simplify cpu-cache interface
2012-02-26 18:26:29 -08:00
Andrew Waterman
ad713a5d83
fix icache ram depth; new chisel
2012-02-26 17:51:46 -08:00
Yunsup Lee
f3bb02b2ea
refactored dmem arbiter
2012-02-26 17:38:08 -08:00
Huy Vo
93f41d3359
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-26 17:24:23 -08:00
Huy Vo
5b0f7ccf68
updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
2012-02-26 17:24:08 -08:00
Yunsup Lee
766a039ffe
small changes to the dtlb arbiter
2012-02-26 16:19:50 -08:00
Daiwei Li
69260756bd
change ppn and vpn in dtlb from ufix to bits
2012-02-26 02:54:31 -08:00
Yunsup Lee
49efe4b744
now vu steals cycles from the fpu's fma alu
2012-02-26 01:55:07 -08:00
Daiwei Li
47dbc2a417
head should be working again
2012-02-26 00:30:50 -08:00
Daiwei Li
569698b824
dtlb now arbitrates between cpu, vec, and vec pf
2012-02-25 22:05:30 -08:00
Yunsup Lee
94ba32bbd3
change package name and sbt project name to rocket
2012-02-25 17:09:26 -08:00
Yunsup Lee
946e0c6e4e
add vector exception infrastructure
2012-02-25 16:37:56 -08:00
Yunsup Lee
3839e3a318
massive refactoring of vector constants
2012-02-25 15:55:36 -08:00
Henry Cook
3980120279
More stylish bundle param names, some hub progress
2012-02-25 15:27:53 -08:00
Henry Cook
db6d480778
Better foldR
2012-02-25 15:27:09 -08:00
Henry Cook
df97de0fd3
Better abstraction of data bundles
2012-02-25 12:57:01 -08:00
Henry Cook
4fa31b300b
Added popcount util
2012-02-25 12:57:01 -08:00
Yunsup Lee
a1600d95db
fix bug related to waddr and wdata in wb stage
...
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
2012-02-25 12:21:10 -08:00
Yunsup Lee
137fd62007
refactor cpfences
2012-02-25 12:20:36 -08:00
Andrew Waterman
4121fb178c
clean up mul/div interface; use VU mul if HAVE_VEC
2012-02-24 19:22:35 -08:00
Andrew Waterman
b3a3289d34
fix (?) external memory request nack interface
2012-02-24 01:42:33 -08:00
Daiwei Li
477f3cde02
added prefetch queues for vu
2012-02-24 00:44:13 -08:00
Yunsup Lee
63939efd0c
fix ctrl vec iface hookup - final
2012-02-23 23:03:44 -08:00
Yunsup Lee
bf1e643913
fix ctrl vec iface hookup
2012-02-23 22:55:25 -08:00
Andrew Waterman
7b3cce79e3
allocate a primary miss on a prefetch
2012-02-23 22:40:24 -08:00
Yunsup Lee
2ea309cf80
bug fixes to ctrl_vec
2012-02-23 22:35:05 -08:00
Yunsup Lee
91a0bb6f61
add vector prefetch queues
2012-02-23 22:30:38 -08:00
Andrew Waterman
012028efaa
fix fpga build
2012-02-23 22:19:38 -08:00
Henry Cook
52da831aa3
finished xact_finish and xact_abort transactors in coherence hub
2012-02-23 18:12:50 -08:00
Henry Cook
1c1ce7d60b
finished xact_rep transactor in coherence hub
2012-02-23 17:50:02 -08:00
Andrew Waterman
5332bab6f1
expose FMA ports outside of FPU (for the VU)
2012-02-23 17:39:34 -08:00
Andrew Waterman
6ceaa0e80a
correct and simplify replay_next logic
2012-02-23 16:52:52 -08:00
Andrew Waterman
f939088be1
move datapath control signals into control unit
...
because that's where control signals go
2012-02-23 16:52:52 -08:00
Yunsup Lee
e53792a1eb
fix bug in rocket's vector datapath related to wakeup
2012-02-23 10:14:14 -08:00
Andrew Waterman
7c929afe2b
HTIF now controls CPU reset
2012-02-22 19:30:03 -08:00
Andrew Waterman
3eebf40310
nack CPU requests during any replay
2012-02-22 18:37:13 -08:00
Henry Cook
62837537f4
Improved TileIO organization, beginnings of hub implementation
2012-02-22 18:24:52 -08:00
Henry Cook
24a32c2811
Refining tilelink interface
2012-02-22 12:15:47 -08:00
Henry Cook
18bd0c232b
Added coherence message type enums
2012-02-22 12:15:47 -08:00
Daiwei Li
22f8dd0994
Hook up resp_type to vector unit
2012-02-21 18:20:32 -08:00
Andrew Waterman
cfd79c731b
add resp_type to ext_mem interface
2012-02-21 17:42:00 -08:00
Andrew Waterman
9a80adef50
only instantiate VI$ if HAVE_VEC
2012-02-21 15:53:19 -08:00
Andrew Waterman
c8f768c8b3
fix AMO replay bug
...
like the recent AMO bug fix, but affects stores too. oops.
2012-02-21 14:39:54 -08:00
Andrew Waterman
d5608b2728
fix AMO replay bug
...
didn't check for structural hazard on AMO unit
if a replay was initiated one cycle before before
a hit-under-miss AMO was issued
2012-02-21 01:02:16 -08:00
Andrew Waterman
6135615104
unify cache backend interfaces; generify arbiter
2012-02-20 00:51:48 -08:00
Andrew Waterman
7034c9be65
new htif protocol and implementation
...
You must update your fesvr and isasim!
2012-02-19 23:15:45 -08:00
Andrew Waterman
9af86633d7
invalidate I$ prefetcher when invalidating I$
2012-02-17 17:56:01 -08:00
Henry Cook
e555fd3fc4
Abstract class for coherence policies
2012-02-16 12:59:38 -08:00
Henry Cook
d46e59a16d
Abstract base nbcache class
2012-02-16 12:34:51 -08:00
Henry Cook
124efe5281
Replace nbcache manipulation of meta state bits with abstracted functions
2012-02-16 10:43:40 -08:00
Henry Cook
619929eba1
Added coherence tile function defs, with traits and constants
2012-02-16 00:16:45 -08:00
Andrew Waterman
1b5e39e7fc
fix bug in BTB
...
a BTB update followed by a taken branch could cause incorrect control flow.
2012-02-15 21:36:08 -08:00
Andrew Waterman
fc5ba769da
disable vector unit by default
2012-02-15 18:58:41 -08:00
Andrew Waterman
8b3b3abd3d
fix external memory request nack logic
2012-02-15 18:57:40 -08:00
Andrew Waterman
fe2c1d1321
add vec->ctrl fences
2012-02-15 18:31:19 -08:00
Yunsup Lee
82cd3625c2
add in vackq interface
2012-02-15 17:53:24 -08:00
Andrew Waterman
c13524ad3a
fix vcmdq full replay logic
2012-02-15 17:49:12 -08:00
Yunsup Lee
258d050e1b
add stall logic for vector command queues
2012-02-15 14:48:41 -08:00
Yunsup Lee
32bdf5098a
refactor vector control logic & datapath in the rocket core
2012-02-15 13:30:22 -08:00
Yunsup Lee
7c11c1406c
vector-vector add working!
2012-02-15 02:28:07 -08:00
Yunsup Lee
6bdf9dc513
hwacha integration: now it compiles correctly!
2012-02-14 23:34:57 -08:00
Yunsup Lee
a51c7cc927
new build system with updated chisel, hwacha
2012-02-14 19:43:59 -08:00
Andrew Waterman
0ec7767c13
declaring success on FPU for now
2012-02-14 19:11:57 -08:00
Andrew Waterman
297223a13c
squash subsequent external mem request after nack
2012-02-14 15:12:16 -08:00
Andrew Waterman
38c67e5a9e
add fmin.[s|d] and fmax.[s|d]
2012-02-14 06:37:18 -08:00
Andrew Waterman
ee9fc10668
add fcvt.s.d, fcvt.d.s
2012-02-14 06:03:43 -08:00
Andrew Waterman
ce202c73d1
add fsgnj[n|x].[s|d]
2012-02-14 04:24:35 -08:00
Andrew Waterman
1d604bcd49
remove top-level Makefile
...
new, simpler build instructions are in the README.
note that for "make run-asm-tests-debug" you need to update your fesvr.
2012-02-14 02:53:43 -08:00
Andrew Waterman
15dc2d8c40
add fp writeback arbitration logic
2012-02-14 00:32:25 -08:00
Henry Cook
0671a99712
NBcache works with associativities other than powers of 2
2012-02-13 21:44:32 -08:00
Henry Cook
6d36168183
Fixed two associative nbcache bugs, one in amo replays and one in the flush unit
2012-02-13 21:44:32 -08:00
Andrew Waterman
0366465cb1
parameterize the scoreboards
2012-02-13 18:12:23 -08:00
Andrew Waterman
6c2d8a37ae
remove a partial update that makes chisel barf
...
chisel regards it as a combinational loop, even though it isn't.
2012-02-13 16:45:29 -08:00
Andrew Waterman
c78c738f60
minor cleanups
2012-02-13 03:13:49 -08:00
Andrew Waterman
b5a19a54a3
add fcvt.[s|d].[w|l][u]
2012-02-13 02:01:26 -08:00
Andrew Waterman
a4a9d2312c
add fcvt.[w|l][u].[s|d], f[eq|lt|le].[s|d]
2012-02-13 01:30:01 -08:00
Andrew Waterman
069037ff3a
add FP recoding
2012-02-12 23:31:50 -08:00
Andrew Waterman
25ecfb9bbc
clean up caches
...
- remove incompatible blocking D$
- remove direct-mapped nonblocking cache
2012-02-12 20:32:06 -08:00
Andrew Waterman
08b6517a23
add FP ops mftx, mxtf, mtfsr, mffsr
2012-02-12 20:12:53 -08:00
Andrew Waterman
9bb1558a34
WIP on FPU
2012-02-12 04:36:01 -08:00
Andrew Waterman
50a283d311
move store data generation into EX stage
...
doing so removes it from the critical path of FP store unrecoding.
2012-02-12 01:35:55 -08:00
Andrew Waterman
725190d0ee
update to new chisel
2012-02-11 17:20:33 -08:00
Andrew Waterman
f8b937d590
fix 32-bit divider bug
...
thanks, torture!
also, tidied up the code a bit.
2012-02-09 03:47:59 -08:00
Andrew Waterman
03ee49f424
fix 32-bit AMOs to upper halves of 64-bit words
...
thanks, torture!
2012-02-09 03:31:47 -08:00
Yunsup Lee
f47d888feb
vvcfgivl and vsetvl works
2012-02-09 02:35:21 -08:00
Andrew Waterman
92493ad153
fix mul/div kill bug
...
occasionally, an in-progress multiply or divide could be
erroneously killed, tying up the register forever.
2012-02-09 02:26:03 -08:00
Andrew Waterman
128ec567ed
make BTB fully associative; don't use it for JALR
...
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
2012-02-09 01:34:00 -08:00
Yunsup Lee
fcc8081c4d
hook up the vector command queue
2012-02-09 01:28:16 -08:00
Andrew Waterman
8b6b0f5367
add external memory request interface for vec unit
2012-02-08 22:30:45 -08:00
Yunsup Lee
9285a52f25
initial vu integration
2012-02-08 21:43:45 -08:00
Andrew Waterman
10b5a0006c
fix mul/div to rd=0
2012-02-08 20:11:57 -08:00
Andrew Waterman
a1855b12c2
clean up queues
2012-02-08 17:55:05 -08:00
Andrew Waterman
990e3a1b34
fix fpu port direction bug
2012-02-08 15:19:26 -08:00
Andrew Waterman
b3f6f9a5fd
fix BTB misprediction check for negative addresses
...
also index BTB with PC, not PC+4
2012-02-08 15:05:28 -08:00
Andrew Waterman
e9da2cf66a
improve id/ex datapath
...
move operand selection into decode stage; simplify bypassing
2012-02-08 06:47:26 -08:00
Andrew Waterman
d471a8b2da
arbitrate for LLFU writebacks in MEM stage
2012-02-08 04:21:05 -08:00
Andrew Waterman
ebed56500e
fix mul/wb hazard checks
...
I erroneously assumed that those instructions set id_wen.
2012-02-08 01:56:11 -08:00
Andrew Waterman
5403d069e9
add fp loads/stores
2012-02-07 23:54:25 -08:00
Christopher Celio
1be9d15944
Fixed bug regarding case sensitivity regarding ioICache,ioDCache
2012-02-07 14:07:42 -08:00
Andrew Waterman
fde8e3b696
clean up bypassing/hazard checking a bit
2012-02-06 17:26:45 -08:00
Henry Cook
41c4e10c37
Workaround for another frakking extraction error in the C backend. C and VLSI backends now both boot kernel with associativity on
2012-02-02 21:53:57 -08:00
Andrew Waterman
99a959e6b1
remove pc+4 piperegs and add new ex pc+4 adder
2012-02-02 13:33:27 -08:00
Andrew Waterman
01a156eb98
make # of dcache lines configurable
2012-02-01 21:11:45 -08:00
Andrew Waterman
b1bbf56b74
clean up wb->id bypass
2012-02-01 16:41:18 -08:00
Henry Cook
c5a4eaa0a1
Associative cache, boots kernel
2012-02-01 13:26:04 -08:00
Henry Cook
281abfbccb
New Mux1H constructor
2012-02-01 13:24:28 -08:00
Andrew Waterman
38c9105ea1
fix mul/div deadlock bug
...
If independent multiplies or independent divides were issued
back-to-back, the second wouldn't execute, causing the register
to be busy forever.
2012-01-30 21:14:28 -08:00
Andrew Waterman
bd241ea237
fix when badvaddr is set
2012-01-30 17:15:42 -08:00
Andrew Waterman
a96c92f58d
enable amomin[u]/amomax[u
2012-01-26 20:45:04 -08:00
Andrew Waterman
a7999d4525
don't flush I$ unless fence.i commits
...
otherwise, we might not make forward progress.
2012-01-26 20:37:09 -08:00
Andrew Waterman
32f5f420f3
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-01-26 20:12:42 -08:00
Andrew Waterman
41855a6d47
fix missing "otherwise" in PCR file
...
this fixes timer interrupts for VLSI backend.
2012-01-26 19:33:55 -08:00
Andrew Waterman
7172ddd050
don't flush pipeline after MFPCR
2012-01-24 18:40:08 -08:00
Andrew Waterman
97c379f1d7
made I$ associative
2012-01-24 16:51:30 -08:00
Henry Cook
aa3465699b
LFSR now a util
2012-01-24 15:26:19 -08:00
Andrew Waterman
7f26fe2c44
make icache size parameterizable
2012-01-24 15:13:49 -08:00
Henry Cook
8229d65adf
Associative cache passes asm tests and bmarks with power of 2 associativities (including 1)
2012-01-24 11:41:44 -08:00
Andrew Waterman
9e6b86fe85
Fix a nasty replay bug
...
If a mispredicted branch was followed by an instruction dependent
on a load that missed in the cache, the mispredicted path would
be executed rather than the correct path. Fail.
Example broken code:
lw x2, 0(x2) # cache miss
beq x3, x0, somewhere # mispredicted branch
move x4, x2 # wrong-path instruction dependent on load miss
2012-01-24 03:40:01 -08:00
Andrew Waterman
06fdf79dab
fix long-latency writeback arbitration bug
2012-01-24 00:56:47 -08:00
Andrew Waterman
f1c355e3cd
check pc/effective address sign extension
2012-01-24 00:15:17 -08:00
Andrew Waterman
a5a020f97b
update chisel and remove SRAM_READ_LATENCY
2012-01-23 20:59:38 -08:00
Henry Cook
8766438bb9
Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
2012-01-23 17:09:23 -08:00
Andrew Waterman
e7bf07d55e
fix AMO replay bug
2012-01-23 15:35:53 -08:00
Andrew Waterman
d59bddfbf1
fix I$ miss replay bug
2012-01-21 20:42:13 -08:00
Andrew Waterman
31c56228e2
add missing "otherwise"
2012-01-21 20:13:15 -08:00
Henry Cook
97f0852b17
DM cache with assoc-aware subunits passes all asm and bmarks
2012-01-18 17:53:26 -08:00
Henry Cook
8623d58724
split into two caches, compiles
2012-01-18 17:09:35 -08:00
Henry Cook
29ed8eb31a
More utils for nbdcache
2012-01-18 17:09:35 -08:00
Henry Cook
7e25749581
Groundwork for assoc cache implementation
2012-01-18 17:09:35 -08:00
Andrew Waterman
07f184df2f
adhere to new chisel c naming convention
2012-01-18 15:23:21 -08:00
Henry Cook
1d76255dc1
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 14:39:57 -08:00
Andrew Waterman
e4cf6391d7
fix i$ miss pathology and badvaddr bug
2012-01-17 23:47:35 -08:00
Andrew Waterman
0369b05deb
move replays to writeback stage
2012-01-17 21:12:31 -08:00
Andrew Waterman
1c8f496811
fix fpga build
2012-01-13 20:04:11 -08:00
Andrew Waterman
addfe55735
add FPGA memory generator script
2012-01-13 18:19:08 -08:00
Andrew Waterman
acf3134e80
minor control logic cleanup
2012-01-12 14:19:18 -08:00
Andrew Waterman
4807d7222b
use replay to handle I$ misses
...
this eliminates a long path in the fetch stage
2012-01-11 19:20:20 -08:00
Andrew Waterman
1a7bfd4350
remove icache req_rdy signal
2012-01-11 18:27:11 -08:00
Andrew Waterman
bcb55e581a
remove host.start signal, use reset instead
2012-01-11 17:49:32 -08:00
Andrew Waterman
92dda102b6
slight control logic cleanup
2012-01-11 16:56:40 -08:00
Andrew Waterman
938b142d64
require writes to memory to be uninterrupted
2012-01-03 18:41:53 -08:00
Andrew Waterman
142dfc6e07
made tohost/fromhost 64 bits wide
2012-01-03 15:09:08 -08:00
Andrew Waterman
20aee36c96
move PCR writes to WB stage
2012-01-02 15:42:39 -08:00
Andrew Waterman
3045b33460
remove second RF write port
...
load miss writebacks are treated like mul/div now.
2012-01-02 02:51:30 -08:00
Andrew Waterman
ffe23a1ee8
fix WAW hazard handling
2012-01-02 00:25:11 -08:00
Andrew Waterman
eb657dd250
reduce superfluous replays
...
we only replay after a cache miss if we mis-scheduled the use of a load.
2012-01-01 21:28:38 -08:00
Andrew Waterman
efc623cc36
validate BTB address and use BTB for J/JAL/JR/JALR
...
even if we weren't using the BTB for JR/JALR, we'd need to
flush the BTB on FENCE.I and on context switches, but
validating its result suffices instead.
2012-01-01 17:04:14 -08:00
Andrew Waterman
2f8fcebea0
remove datapath register resets resets
2012-01-01 16:09:40 -08:00
Andrew Waterman
f9160c53cf
fixes for correct verilog generation
2011-12-29 23:46:21 -08:00
Andrew Waterman
1028ff7d9b
fix multiplier bug
2011-12-29 23:45:09 -08:00
Andrew Waterman
d65e1a2eee
vlsi verilog compiles now but doesn't simulate
2011-12-20 22:08:27 -08:00
Andrew Waterman
38ea10a5f4
parameterized multiplier unrolling
2011-12-20 04:18:28 -08:00
Andrew Waterman
733fc8e65e
booth multiplier
2011-12-20 03:49:07 -08:00
Andrew Waterman
b5a8b6dc73
fix divider for RV32
2011-12-19 16:57:53 -08:00
Andrew Waterman
bcceb08373
add dummy mul_rdy signal
2011-12-17 07:30:47 -08:00
Andrew Waterman
96c78829b4
improve ALU and fix revealed emulator bug
2011-12-17 07:20:32 -08:00
Andrew Waterman
82700cad72
fix multiplier for rv32
2011-12-17 07:20:00 -08:00
Andrew Waterman
a8d0cd95e6
hellacache now works
2011-12-17 03:26:11 -08:00
Andrew Waterman
56c4f44c2a
hellacache returns!
...
but AMOs are unimplemented.
2011-12-12 06:49:39 -08:00
Yunsup Lee
0ea2704b80
new mftx instruction format
2011-12-12 03:23:12 -08:00
Andrew Waterman
8308345364
work in progress on hellacache
2011-12-10 07:01:47 -08:00
Andrew Waterman
ce201559f3
Support cache->cpu nacks one cycle after request
2011-12-10 00:42:09 -08:00
Andrew Waterman
c01e1f1cef
Don't replay from EX stage.
...
EX replays are now handled from MEM. We may move them to WB.
2011-12-09 19:42:58 -08:00
Andrew Waterman
218f63e66e
code cleanup/parameterization
2011-12-09 00:42:43 -08:00
Andrew Waterman
a87ad06780
Automatically infer rocketCAM address width
2011-12-06 02:05:40 -08:00
Rimas Avizienis
fa784d1d7d
made setReadLatency argument a parameter defined in consts.scala
2011-12-05 00:33:17 -08:00
Rimas Avizienis
ff95cacb55
icache/dcache tag+data arrays now implemented using Mem4()
...
however there seems to be a bug - readLatency needs to be set to 0
for C model to work, and 1 for Verilog model.
2011-12-04 01:18:38 -08:00
Rimas Avizienis
e894b79870
caches now use Mem4() memories for tag+data arrays
2011-12-03 19:41:15 -08:00
Rimas Avizienis
c580180b66
tweaks to cache/SRAM interface for TSMC65 SRAMs
2011-12-02 02:01:08 -08:00
Rimas Avizienis
e70b41241c
changed branch addr generation to get it off critical path
2011-12-02 01:56:17 -08:00
Rimas Avizienis
cf1965493b
renamed SRAM modules to match TSMC65 MC generated SRAMs
2011-12-01 13:14:33 -08:00
Rimas Avizienis
da2fdf4f85
fixed console i/o
2011-11-30 22:51:59 -08:00
Rimas Avizienis
b2894671f6
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2011-11-30 21:55:13 -08:00
Rimas Avizienis
bc44572d99
bugfixes due to new hcl jar file
2011-11-30 21:54:55 -08:00
Andrew Waterman
8f3927fdfa
queue data type is now templated
2011-11-30 18:08:26 -08:00
Rimas Avizienis
11f0e3daf4
more cleanup
2011-11-18 00:17:30 -08:00
Rimas Avizienis
c42d8149b7
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
2011-11-17 23:50:45 -08:00
Rimas Avizienis
5a322ff00c
fixed dtlb bug (swapped r/w permissions), added fake mtfsr/mffsr/fld/fst instructions
2011-11-17 11:17:37 -08:00
Rimas Avizienis
80b4253318
fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
2011-11-16 02:04:28 -08:00
Rimas Avizienis
886857fa47
writes of PC weren't being sign extended
2011-11-15 18:07:36 -08:00
Rimas Avizienis
fc0f20643a
cleanup
2011-11-15 18:06:41 -08:00
Rimas Avizienis
ae98956e6b
more amo fixes, added more options to testharness to control debug messages
2011-11-15 02:43:51 -08:00
Rimas Avizienis
82a636ff55
AMOADD, AMOAND, AMOOR, AMOSWAP working
2011-11-15 00:51:45 -08:00
Rimas Avizienis
48cec01710
updated riscv-bmarks and riscv-tests to build with new toolchain
2011-11-15 00:11:22 -08:00
Rimas Avizienis
db87924fbf
made eret instruction take an illegal inst exception when ET is set
2011-11-14 14:35:10 -08:00
Rimas Avizienis
cd6e463320
added ei and di instructions
2011-11-14 13:48:49 -08:00
Rimas Avizienis
b791010bb1
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 04:13:13 -08:00
Rimas Avizienis
890bfa7c48
added IPIs and timer interrupts
2011-11-14 03:24:02 -08:00
Rimas Avizienis
5b29765917
synced up with supervisor mode state in latest ISA simulator
2011-11-14 01:37:20 -08:00
Rimas Avizienis
9d3471a569
more cache fixes, more test harness debug output
2011-11-13 23:32:18 -08:00
Rimas Avizienis
67c7e7e28f
cache/tlb bugfixes, increased memory size to 256meg
2011-11-13 13:06:35 -08:00
Rimas Avizienis
29d44b8bc5
fixed typo that broke illegal instruction exception
2011-11-13 01:17:33 -08:00
Rimas Avizienis
7b3c34a341
regenerated instruction encodings using parse-opcodes
2011-11-13 00:59:02 -08:00
Rimas Avizienis
44419511b7
timer interrupt fixes
2011-11-13 00:32:08 -08:00
Rimas Avizienis
345f950eff
added timer interrupt support
2011-11-13 00:27:57 -08:00
Rimas Avizienis
5f4b15b809
added ld/st misaligned exceptions
2011-11-13 00:03:17 -08:00
Rimas Avizienis
fbd44ea936
added checks for addresses > physical memory size, increased memsize to 64M
2011-11-12 23:39:43 -08:00
Rimas Avizienis
35af912bd2
cache optimizations, cleanup, and testharness improvement
2011-11-12 22:13:29 -08:00
Rimas Avizienis
91c252ad08
fixing output enable signals for data/tag SRAMs
2011-11-12 15:47:47 -08:00
Rimas Avizienis
83d90c4dab
more itlb/dtlb/ptw fixes
2011-11-12 15:00:45 -08:00
Rimas Avizienis
73416f224b
more tlb/ptw debugging
2011-11-12 00:25:06 -08:00
Rimas Avizienis
44926866b7
updated itlb
2011-11-11 18:48:34 -08:00
Rimas Avizienis
a1ce908541
dcache/dtlb overhaul
2011-11-11 18:18:47 -08:00
Rimas Avizienis
e4fa94aa27
checkpoint
2011-11-10 17:41:22 -08:00
Rimas Avizienis
f86d5b1334
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
2011-11-10 11:26:13 -08:00
Rimas Avizienis
4bd0263a4a
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 03:38:59 -08:00
Rimas Avizienis
603ede8bfe
access faults now write badvaddr PCR register with faulting address
2011-11-10 02:46:09 -08:00
Rimas Avizienis
36aa4bcc9d
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 02:26:26 -08:00
Rimas Avizienis
fbfa356d2a
fixed eret instruction
2011-11-10 00:37:00 -08:00
Rimas Avizienis
62407b4668
more tlb/ptw fixes
2011-11-10 00:23:29 -08:00
Rimas Avizienis
6664af3bc0
cleanup before adding dtlb
2011-11-09 23:27:29 -08:00
Rimas Avizienis
9aca403aa8
more itlb integration & cleanup
2011-11-09 23:18:14 -08:00
Rimas Avizienis
c29d2821b4
cleanup, fixes, initial commit for dtlb.scala
2011-11-09 21:54:11 -08:00
Rimas Avizienis
e96430d862
integrating ITLB & PTW
2011-11-09 14:52:17 -08:00
Rimas Avizienis
7130edac8d
fix for flushed div/mul instructions
2011-11-07 01:03:47 -08:00
Rimas Avizienis
9d63087eb2
changed caches to use separate sram modules for tag and data arrays
2011-11-07 00:58:25 -08:00
Rimas Avizienis
4d64099103
cleanup
2011-11-04 20:52:21 -07:00
Rimas Avizienis
2db9ee12bc
fixed eret instruction, hello world runs
2011-11-04 15:57:08 -07:00
Rimas Avizienis
4459935554
dcache fixes - all tests and ubmarks pass, hello world still broken
2011-11-04 15:40:41 -07:00
Rimas Avizienis
3a02028a35
fixes to exception and dcache miss/blocked handling
2011-11-02 13:32:32 -07:00
Rimas Avizienis
7a528d6255
fixes for div/mul hazard checking + cleanup
2011-11-01 23:14:34 -07:00
Rimas Avizienis
d8ffecf565
dcache fix
2011-11-01 22:10:06 -07:00
Rimas Avizienis
7479e085ec
dcache loads working - 1/2 cycle load/use delay depending on load type
2011-11-01 22:04:45 -07:00
Rimas Avizienis
3b3d988fde
dcache loads working - 1/2 cycle load/use delay depending on load type
2011-11-01 21:25:52 -07:00
Rimas Avizienis
2b67eee683
pipeline changes for replay on dcache miss
2011-11-01 19:05:27 -07:00
Rimas Avizienis
08b89e7710
interface cleanup, major pipeline changes
2011-11-01 17:59:27 -07:00
Rimas Avizienis
ace4c9d13c
dcache fixes
2011-10-31 17:17:36 -07:00
Rimas Avizienis
65f8b2461c
dcache tweaks
2011-10-31 16:47:31 -07:00
Rimas Avizienis
172e561a78
added once cycle latency store pipelined d$
2011-10-31 15:37:37 -07:00
Rimas Avizienis
c06e2d16e4
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-25 23:02:47 -07:00