Yunsup Lee
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d4ec7ff4d9
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refined vector exception interface
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2012-03-03 16:11:54 -08:00 |
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Yunsup Lee
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e28a551368
|
refactor code related to vector exceptions
- revisied interfaces
- new instructions
|
2012-03-03 15:15:00 -08:00 |
|
Yunsup Lee
|
54baa0713c
|
hack fence.g.cv to support waiting the control processor
|
2012-03-02 02:10:26 -08:00 |
|
Yunsup Lee
|
1054cec087
|
add vec countq interface
|
2012-03-02 00:43:32 -08:00 |
|
Yunsup Lee
|
8678b3d70c
|
clean up ioDecoupled/ioPipe interface
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2012-03-01 20:48:46 -08:00 |
|
Yunsup Lee
|
6847160343
|
refactor arbiter priorities
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2012-03-01 00:22:34 -08:00 |
|
Yunsup Lee
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f641b44fb8
|
changes after the module uniquify bug fix
|
2012-02-29 22:00:59 -08:00 |
|
Yunsup Lee
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3d96a2d4f0
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add fpu.dec.wen := false when HAVE_FPU is turned off
|
2012-02-27 14:00:58 -08:00 |
|
Yunsup Lee
|
bfd0ae125e
|
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
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2012-02-26 23:46:51 -08:00 |
|
Andrew Waterman
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e12b9eae93
|
remove ext_mem interface
hindsight is 20/20
|
2012-02-26 18:53:39 -08:00 |
|
Andrew Waterman
|
2d04664a98
|
simplify cpu-cache interface
|
2012-02-26 18:26:29 -08:00 |
|
Yunsup Lee
|
f3bb02b2ea
|
refactored dmem arbiter
|
2012-02-26 17:38:08 -08:00 |
|
Yunsup Lee
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766a039ffe
|
small changes to the dtlb arbiter
|
2012-02-26 16:19:50 -08:00 |
|
Yunsup Lee
|
49efe4b744
|
now vu steals cycles from the fpu's fma alu
|
2012-02-26 01:55:07 -08:00 |
|
Daiwei Li
|
47dbc2a417
|
head should be working again
|
2012-02-26 00:30:50 -08:00 |
|
Daiwei Li
|
569698b824
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dtlb now arbitrates between cpu, vec, and vec pf
|
2012-02-25 22:05:30 -08:00 |
|
Yunsup Lee
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94ba32bbd3
|
change package name and sbt project name to rocket
|
2012-02-25 17:09:26 -08:00 |
|
Yunsup Lee
|
946e0c6e4e
|
add vector exception infrastructure
|
2012-02-25 16:37:56 -08:00 |
|
Andrew Waterman
|
4121fb178c
|
clean up mul/div interface; use VU mul if HAVE_VEC
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2012-02-24 19:22:35 -08:00 |
|
Daiwei Li
|
477f3cde02
|
added prefetch queues for vu
|
2012-02-24 00:44:13 -08:00 |
|
Andrew Waterman
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5332bab6f1
|
expose FMA ports outside of FPU (for the VU)
|
2012-02-23 17:39:34 -08:00 |
|
Andrew Waterman
|
7c929afe2b
|
HTIF now controls CPU reset
|
2012-02-22 19:30:03 -08:00 |
|
Daiwei Li
|
22f8dd0994
|
Hook up resp_type to vector unit
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2012-02-21 18:20:32 -08:00 |
|
Andrew Waterman
|
7034c9be65
|
new htif protocol and implementation
You must update your fesvr and isasim!
|
2012-02-19 23:15:45 -08:00 |
|
Yunsup Lee
|
82cd3625c2
|
add in vackq interface
|
2012-02-15 17:53:24 -08:00 |
|
Yunsup Lee
|
32bdf5098a
|
refactor vector control logic & datapath in the rocket core
|
2012-02-15 13:30:22 -08:00 |
|
Yunsup Lee
|
7c11c1406c
|
vector-vector add working!
|
2012-02-15 02:28:07 -08:00 |
|
Yunsup Lee
|
6bdf9dc513
|
hwacha integration: now it compiles correctly!
|
2012-02-14 23:34:57 -08:00 |
|
Andrew Waterman
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15dc2d8c40
|
add fp writeback arbitration logic
|
2012-02-14 00:32:25 -08:00 |
|
Andrew Waterman
|
069037ff3a
|
add FP recoding
|
2012-02-12 23:31:50 -08:00 |
|
Andrew Waterman
|
08b6517a23
|
add FP ops mftx, mxtf, mtfsr, mffsr
|
2012-02-12 20:12:53 -08:00 |
|
Andrew Waterman
|
9bb1558a34
|
WIP on FPU
|
2012-02-12 04:36:01 -08:00 |
|
Andrew Waterman
|
128ec567ed
|
make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
|
2012-02-09 01:34:00 -08:00 |
|
Yunsup Lee
|
fcc8081c4d
|
hook up the vector command queue
|
2012-02-09 01:28:16 -08:00 |
|
Andrew Waterman
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8b6b0f5367
|
add external memory request interface for vec unit
|
2012-02-08 22:30:45 -08:00 |
|
Yunsup Lee
|
9285a52f25
|
initial vu integration
|
2012-02-08 21:43:45 -08:00 |
|
Andrew Waterman
|
5403d069e9
|
add fp loads/stores
|
2012-02-07 23:54:25 -08:00 |
|
Andrew Waterman
|
f1c355e3cd
|
check pc/effective address sign extension
|
2012-01-24 00:15:17 -08:00 |
|
Henry Cook
|
8766438bb9
|
Updated chisel removes ^^ from language. Removed from rocket source, updated jar.
|
2012-01-23 17:09:23 -08:00 |
|
Henry Cook
|
1d76255dc1
|
new chisel version jar and find and replace INPUT and OUTPUT
|
2012-01-18 14:39:57 -08:00 |
|
Andrew Waterman
|
1a7bfd4350
|
remove icache req_rdy signal
|
2012-01-11 18:27:11 -08:00 |
|
Andrew Waterman
|
bcb55e581a
|
remove host.start signal, use reset instead
|
2012-01-11 17:49:32 -08:00 |
|
Andrew Waterman
|
92dda102b6
|
slight control logic cleanup
|
2012-01-11 16:56:40 -08:00 |
|
Andrew Waterman
|
142dfc6e07
|
made tohost/fromhost 64 bits wide
|
2012-01-03 15:09:08 -08:00 |
|
Andrew Waterman
|
3045b33460
|
remove second RF write port
load miss writebacks are treated like mul/div now.
|
2012-01-02 02:51:30 -08:00 |
|
Andrew Waterman
|
ffe23a1ee8
|
fix WAW hazard handling
|
2012-01-02 00:25:11 -08:00 |
|
Andrew Waterman
|
56c4f44c2a
|
hellacache returns!
but AMOs are unimplemented.
|
2011-12-12 06:49:39 -08:00 |
|
Andrew Waterman
|
ce201559f3
|
Support cache->cpu nacks one cycle after request
|
2011-12-10 00:42:09 -08:00 |
|
Andrew Waterman
|
c01e1f1cef
|
Don't replay from EX stage.
EX replays are now handled from MEM. We may move them to WB.
|
2011-12-09 19:42:58 -08:00 |
|
Rimas Avizienis
|
da2fdf4f85
|
fixed console i/o
|
2011-11-30 22:51:59 -08:00 |
|