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Commit Graph

39 Commits

Author SHA1 Message Date
Andrew Waterman
d426ecee78 Remove IPI network
This is now provided via MMIO.
2015-11-16 21:52:24 -08:00
Henry Cook
f8594da1d3 depend on external cde library 2015-10-21 18:17:17 -07:00
Henry Cook
7fa3eb95e3 refactor tilelink params 2015-10-14 12:13:37 -07:00
Henry Cook
31be6407ec Removed all traces of params 2015-10-14 00:23:28 -07:00
Andrew Waterman
0fe16ac1c0 Chisel3 compatibility fixes 2015-09-30 14:37:00 -07:00
Howard Mao
8c4ac0f4f3 make sure CSR/SCR data width matches xLen 2015-09-25 12:07:03 -07:00
Howard Mao
bd536d8832 make HTIFModuleIO an anonymous bundle 2015-09-14 12:58:44 -07:00
Howard Mao
21f96f382c split off SCR functionality from HTIF 2015-09-14 12:57:54 -07:00
Howard Mao
bdc6972a8d separate RTC updates from HTIF 2015-09-14 12:56:44 -07:00
Andrew Waterman
05d311c517 Use Vec.apply, not Vec.fill, for type nodes 2015-08-27 09:47:02 -07:00
Andrew Waterman
798ddeb5f5 Chisel3 compatibility: use >>Int instead of >>UInt
The latter doesn't contract widths anymore.
2015-08-04 13:15:17 -07:00
Andrew Waterman
a21979a2fa Bits -> UInt 2015-08-03 18:01:06 -07:00
Andrew Waterman
0e06c941df Chisel3 compatibility fixes 2015-07-23 14:58:46 -07:00
Andrew Waterman
3c0475e08b Add Wire() wrap 2015-07-15 20:24:03 -07:00
Andrew Waterman
55059632c4 Temporarily use HTIF to push RTC value to cores 2015-07-05 16:19:39 -07:00
Henry Cook
90c9ee7b04 fix unalloc putblocks 2015-05-14 12:37:35 -07:00
Henry Cook
ba7a8b1752 TileLink refactor; TileLinkPorts now available. L2Banks no longer have unique ids (suitable for hierarhical P&R). 2015-04-17 16:55:20 -07:00
Henry Cook
9708d25dff Restructure L2 state machine and utilize HeaderlessTileLinkIO 2015-04-06 12:19:51 -07:00
Andrew Waterman
6e540825b2 Use entire 12-bit CSR address 2015-03-14 02:15:24 -07:00
Henry Cook
a1f04386f7 Headerless TileLinkIO and arbiters 2015-03-09 16:34:59 -07:00
Henry Cook
1bed6ea498 New metadata-based coherence API 2015-02-28 17:32:03 -08:00
Henry Cook
3aa030f960 Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor. 2015-02-01 20:37:16 -08:00
Henry Cook
9ef00d187f %s/master/manager/g + better comments 2014-12-29 22:55:58 -08:00
Henry Cook
3026c46a9c Finish adding TLDataBeats to uncore & hub 2014-12-12 17:04:52 -08:00
Henry Cook
82155f333e Major tilelink revision for uncached message types 2014-11-11 17:36:55 -08:00
Yunsup Lee
0b51d70bd2 add LICENSE 2014-09-12 15:31:38 -07:00
Henry Cook
712f3a754d merge in master 2014-09-02 12:34:42 -07:00
Henry Cook
17b2359c9a htif parameters trait 2014-08-24 19:27:58 -07:00
Henry Cook
f411fdcce3 Full conversion to params. Compiles but does not elaborate. 2014-08-08 12:21:57 -07:00
Andrew Waterman
364a6de214 Use Mem instead of Vec[Reg] 2014-05-18 19:26:35 -07:00
Henry Cook
1163131d1e TileLinkIO.GrantAck -> TileLinkIO.Finish 2014-04-26 15:17:05 -07:00
Henry Cook
b1df49ba30 removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants 2014-04-10 12:35:43 -07:00
Henry Cook
fbca7c6bb3 refactor ioMem and associcated constants. merge Aqcuire and AcquireData 2014-04-10 12:35:43 -07:00
Henry Cook
bbf8010230 cleanups supporting uncore hierarchy 2014-01-31 15:59:21 -08:00
Andrew Waterman
3e634aef1d Fix HTIF for cache line sizes other than 64 B 2014-01-22 18:20:36 -08:00
Andrew Waterman
4f1213cb8b Fix Scala integer overflow 2014-01-13 21:45:14 -08:00
Andrew Waterman
acc0d2b06c Only use LSBs for HTIF control regs
For now, at least...
2013-11-25 04:34:16 -08:00
Yunsup Lee
f13d76628b forgot to put htif into uncore package 2013-11-07 15:42:10 -08:00
Yunsup Lee
c350cbd6ea move htif to uncore 2013-11-07 13:19:04 -08:00