Colin Schmidt
cf3c6fa277
add STOP_COND to emulator & match vsim PRINTF_COND
2016-09-09 11:07:17 -07:00
Andrew Waterman
656aa78f7d
Pipeline FMAs more deeply by default
...
Rocket's QoR has improved enough that the FMAs are on the critical
path. This change seems to keep the integer pipeline's logic
paths balanced with the FPU.
2016-09-09 11:06:42 -07:00
Andrew Waterman
eaa4b04ee5
Check D$ store->load collisions more precisely
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Tolerate, for example, a half-word store and a half-word load to
different halves of the same word.
2016-09-09 11:06:42 -07:00
Henry Cook
c4593d2034
Merge pull request #266 from ucb-bar/multinode
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TL2Node: make it possible for {Identity,Output,Input}Node to pass a Vec
2016-09-09 10:17:45 -07:00
Wesley W. Terpstra
c28ca37944
tilelink2: get rid of fragile implicit lazyModule pattern, and support :=
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We can more reliably find the current LazyModule from the LazyModule.stack
2016-09-08 23:06:59 -07:00
Wesley W. Terpstra
b587a409a3
tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec
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In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
2016-09-08 21:34:20 -07:00
Yunsup Lee
176f385b1d
Merge pull request #263 from ucb-bar/intbar
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TL2 Interrupts
2016-09-08 21:33:25 -07:00
Wesley W. Terpstra
48ca478578
Merge branch 'master' into intbar
2016-09-08 21:09:59 -07:00
Wesley W. Terpstra
808a7f60f4
tilelink2 Legacy: it's only an error if it's valid ( #264 )
2016-09-08 21:09:40 -07:00
Wesley W. Terpstra
1b07d53f70
tilelink2 IntNodes: record interrupt ranges in parameters
2016-09-08 18:51:43 -07:00
Richard Xia
9015276958
Use sbt-launch.jar 0.13.12. ( #262 )
2016-09-08 17:26:04 -07:00
Wesley W. Terpstra
66f58cf2d0
tilelink2 RegisterRouter: support new TL2 interrupts
2016-09-08 15:25:50 -07:00
Wesley W. Terpstra
23e896ed5d
tilelink2 IntNodes: support interrupt graphs
2016-09-08 15:25:48 -07:00
Wesley W. Terpstra
d7df7d3109
tilelink2: connect Nodes to LazyModules for better error messages
2016-09-08 15:24:04 -07:00
Wesley W. Terpstra
53987cd9d4
tilelink2 Nodes: support non-Bundle data for io type
2016-09-08 15:19:12 -07:00
Henry Cook
a44fff5d93
Merge pull request #260 from ucb-bar/w1ToClear
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W1 to clear
2016-09-08 14:27:03 -07:00
Wesley W. Terpstra
60a503dc2f
tilelink2 RegField: add a w1ToClear RegField
2016-09-08 14:02:49 -07:00
Wesley W. Terpstra
99b7e734cd
tilelink2 Bundles: fix wrong sink width!
2016-09-08 13:47:40 -07:00
Wesley W. Terpstra
9bfd8c1cf5
TL2 WidthWidget ( #258 )
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* tilelink2 Narrower: support widenening and narrowing on all channels
Be extra careful with the mask transformations
We need to make sure that narrowing or widening do not cause a loss
of information about the operation. The addr_hi+(mask|addr_lo) conversions
are now 1-1, except on D, which should not matter.
* tilelink2 SRAM: work around firrtl SeqMem bug
* tilelink2 WidthWidget: renamed from Narrower (it now converts both ways)
* tilelink2 mask: fix an issue with width=1 data buses
2016-09-08 10:38:38 -07:00
Yunsup Lee
8536a2a47d
Merge pull request #257 from ucb-bar/fix-non-contiguous-mmio-region-routing
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Fix routing in non-contiguous MMIO regions
2016-09-08 00:03:11 -07:00
Howard Mao
62e33527d3
Merge branch 'master' into fix-non-contiguous-mmio-region-routing
2016-09-07 23:35:12 -07:00
Howard Mao
4592558047
Merge pull request #254 from ucb-bar/inferRW
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Turn on the inferRW Firrtl pass
2016-09-07 21:59:05 -07:00
Yunsup Lee
e35e7b2ee3
Fix routing in non-contiguous MMIO regions
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This is a temporary fix, which can generate more hardware than necessary, but this is OK for now, since this code will soon be replaced with tilelink2 code.
2016-09-07 19:28:12 -07:00
Ben Keller
6be569be9f
Turn on the inferRW Firrtl pass
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Without this, all of the memories wind up as two-ported.
2016-09-07 15:27:26 -07:00
Howard Mao
7a6f155b2a
Merge pull request #253 from ucb-bar/use-companion
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only use companion objects for types
2016-09-07 15:07:17 -07:00
Andrew Waterman
7603b86239
Merge branch 'master' into use-companion
2016-09-07 12:56:55 -07:00
Andrew Waterman
58c87bdf32
Merge pull request #245 from ucb-bar/tilelink2.2
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Tilelink2
2016-09-07 12:56:22 -07:00
Colin Schmidt
254f49093c
only use companion objects for types
2016-09-07 12:32:34 -07:00
Andrew Waterman
23d0b31615
Merge branch 'master' into tilelink2.2
2016-09-07 11:47:50 -07:00
Andrew Waterman
02a2439222
Support a degenerate PLIC with no interrupts
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Resolves #249
2016-09-07 11:21:13 -07:00
Colin Schmidt
92718e4b61
fix null statement in vsli_mem_gen ala firrtl#264 ( #252 )
2016-09-07 11:04:36 -07:00
Andrew Waterman
70cfd7ce13
Make DefaultRV32Config be RV32IMAFCS, not RV32IMC
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The latter is more the domain of TinyConfig.
2016-09-07 01:58:25 -07:00
Andrew Waterman
a7f47f3c23
Reduce default BTB size
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The old value 62 seems to have been a typo introduced over 2 years ago
in commit 63bd0b9d2a
. The intent was to
fit the dhrystone working set (rofl) which the new value of 40 does.
2016-09-07 01:51:27 -07:00
Andrew Waterman
9fea4c83da
Add RV32F support
2016-09-07 00:05:39 -07:00
Andrew Waterman
66e9f027e0
Add MuxT to mux on Tuple2 and Tuple3
2016-09-07 00:05:38 -07:00
Andrew Waterman
511cc6c5c5
Evaluate arg to Boolean.option lazily
2016-09-07 00:05:38 -07:00
Andrew Waterman
a0dcd42e80
avoid erroneously setting tags valid during flush
2016-09-07 00:05:38 -07:00
Yunsup Lee
fb05f5a07f
remove parameter ExtIOAddrMapEntries ( #250 )
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with the AddrMap ordering constraint relaxed, this parameter is no longer needed.
2016-09-07 00:05:00 -07:00
Wesley W. Terpstra
d2421654c4
tilelink2: refactor address into addr_hi on ABC and addr_lo on CD
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We need addr_lo in order to properly convert widths.
As part of the refactoring, move all methods out of the Bundles
2016-09-06 23:46:44 -07:00
Yunsup Lee
b76612f357
relax contraint on adding AddrMapEntry to AddrMap ( #248 )
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now you can add them in any order. there's an explicit check at the end to figure out whether there are overlapping regions.
2016-09-06 21:53:55 -07:00
Howard Mao
7504498dff
Merge pull request #247 from ucb-bar/replseqmem_pr
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Bump FIRRTL for Sequential Memories
2016-09-06 17:22:18 -07:00
Megan Wachs
e95fe646a3
mem_gen failure doesn't create the target
2016-09-06 16:29:29 -07:00
Howard Mao
bbef3a8d3e
Merge pull request #246 from ucb-bar/fix-configstring-printout-problem
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fix configstring printout with no memory
2016-09-06 15:31:39 -07:00
Megan Wachs
48098f5e2d
Bump FIRRTL to instantiate Sequential Memory Macros
2016-09-06 14:48:28 -07:00
Megan Wachs
1fec9807f6
allow override of vlsi_mem_gen script
2016-09-06 14:44:12 -07:00
Wesley W. Terpstra
aae4230627
tilelink2: fix bugs found by Megan in Legacy converter
2016-09-06 13:12:33 -07:00
Yunsup Lee
56d81b0034
fix configstring printout with no memory
2016-09-06 10:40:11 -07:00
Wesley W. Terpstra
54ab14cd9d
tilelink2: statically optimize numBeats for simple managers
2016-09-05 22:11:03 -07:00
Wesley W. Terpstra
314d6ebd6f
tilelink2: stricter TransferSizes requirements
2016-09-05 22:10:28 -07:00
Wesley W. Terpstra
56170c605c
tilelink2: be more forgiving in what Legacy TL requires
2016-09-05 21:12:51 -07:00