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Author SHA1 Message Date
Wesley W. Terpstra ca2c709d29 TLBuffer: move TLBufferParams to diplomacy.BufferParams 2017-03-16 15:19:36 -07:00
Wesley W. Terpstra 778c8a5c97 ToAHB: appease AHB VIP 2017-03-16 15:17:05 -07:00
Wesley W. Terpstra 963d244094 unittest: try both aFlow settings of TLToAHB 2017-03-16 15:13:57 -07:00
Wesley W. Terpstra 604a164b97 TLToAHB: rename parameter to aFlow 2017-03-16 15:10:54 -07:00
Wesley W. Terpstra bb49575368 ahb: rewrote TLToAHB to avoid retracting requests on stall 2017-03-16 14:36:30 -07:00
Wesley W. TerpstraandGitHub 625919722c Merge pull request #584 from ucb-bar/ahb-in 
AHB master port support
 2017-03-14 19:28:09 -07:00
Wesley W. Terpstra c95c2ca9c8 AHB: include bridge unit tests 2017-03-14 18:34:21 -07:00
Wesley W. Terpstra 0c5fd76089 ahb: implement a ToTL bridge 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra 7f71df0925 apb: better test coverage 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra 5885bf29b5 axi4: improve test harness 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra d98fd942f1 tilelink2: optimize the supportsX check circuits 2017-03-14 18:34:17 -07:00
Wesley W. Terpstra 3c5c877409 tilelink2: make TLBuffer API more flexible 2017-03-14 14:06:18 -07:00
Wesley W. Terpstra 6fc3ec3d63 tileink2: add a TestRAM; a zero-delay RAM useful for testing 
TLRAM always answers after 1 cycle. We need a RAM that answers in 0.
 2017-03-14 14:06:17 -07:00
Wesley W. TerpstraandAndrew Waterman c847559853 TLB: add a helper API to determine homogeneous page permissions 2017-03-13 14:50:06 -07:00
Wesley W. Terpstra eaf474a081 LFSR: use random intial value of the start register 
We just need to make sure it doesn't initialize randomly stuck at 0.
 2017-03-13 13:17:52 -07:00
Wesley W. Terpstra d2da33e4b1 Fuzzer: use different LFSR seeds based on simulator seed 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra bb6108abd5 Tests: include more random delays 2017-03-11 02:53:43 -08:00
Wesley W. Terpstra 0c7fb87390 TLDelayer: insert noise on invalid cycles 2017-03-11 02:53:43 -08:00
Wesley W. TerpstraandGitHub 43dea38ee9 dcache: we need the bits within the beat so select the right word (#575) 
We now have confirmation that it fixed the problem.
 2017-03-08 00:19:09 -08:00
Wesley W. Terpstra 676974281a rocket: describe dcache scratchpad as memory 2017-03-03 02:54:48 -08:00
Wesley W. Terpstra 1eeaa390c6 diplomacy: output JSON formatted version of DTS 2017-03-03 02:45:11 -08:00
Wesley W. Terpstra 0178248551 diplomacy: evaluate ResourceBindings only once 2017-03-03 02:04:17 -08:00
Wesley W. Terpstra 8e4f348dda rocket: if no MMU, don't print it in DTS 2017-03-03 00:48:26 -08:00
Wesley W. Terpstra 7660be039c rocketchip: add WithTimebase to set RTC frequency 2017-03-03 00:47:50 -08:00
Wesley W. Terpstra 57a329408c PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0 2017-03-03 00:28:55 -08:00
Wesley W. TerpstraandGitHub 46369850cf Merge pull request #567 from ucb-bar/dts 
Dts - Device Tree Output
 2017-03-02 21:51:51 -08:00
Wesley W. Terpstra 4535de2669 rocket: use diplomatic interrupts 
This makes it possible for the PLIC to work with heterogenous cores.
 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra d3c5318714 build: remove the now obsolete config string 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra 93ca555c20 IntXing: support configurable sync depth 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra 637bc6c3a7 coreplex: pretty print discontiguous ranges properly 2017-03-02 21:19:23 -08:00
Wesley W. Terpstra 7ff9f88ad7 rocket: connect interrupt map for Plic+Clint 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra 38489ad9b0 tilelink2: bring IntNode parameters up to the current standard 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra 5bd9f18e5b rocket: add dts cpu description 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra cfd367248f rocketchip: add blind ports to DTS 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra 9a5e2e038b uncore: add DTS meta-data for devices 2017-03-02 21:19:22 -08:00
Wesley W. Terpstra 0b950b5938 coreplex: bind assigned resources 2017-03-02 21:19:19 -08:00
Wesley W. Terpstra 7f6a250dbf tilelink2: add hooks for Resources 2017-03-02 21:19:19 -08:00
Wesley W. Terpstra e322692d16 diplomacy: add DeviceTree renderer 2017-03-02 21:19:14 -08:00
Wesley W. Terpstra c01a74f4a0 diplomacy: add AddressRange conversion to/from AddressSet 2017-03-02 11:14:28 -08:00
Wesley W. Terpstra bb70b1a3c3 diplomacy: add resource tracking 2017-03-02 11:14:28 -08:00
Wesley W. TerpstraandGitHub fd972f5c67 icache: back-pressure is unnecessary (#564) 
* icache: back-pressure is unnecessary
* icache: require that the response arrives after the request
 2017-02-24 21:01:56 -08:00
Wesley W. Terpstra c01aec9259 tilelink2: support unused IntXing 2017-02-22 18:41:06 -08:00
Wesley W. Terpstra 735e4f8ed6 diplomacy: use HeterogeneousBag instead of Vec 
This makes it possible for the bundles to have different widths.

Previously, we had to widen all the bundles passing through a node
to the widest of all the possibilities.  This would mean that if
you had two source[] fields, they end up the same.
 2017-02-22 17:05:22 -08:00
Wesley W. TerpstraandGitHub 6ea35125d4 Merge pull request #556 from ucb-bar/rational-config 
Rational config
 2017-02-17 20:31:56 +01:00
Wesley W. Terpstra 9153a9a733 ClockDivider: add docs to appease the reviewer 
... even though this means a delay of 1:30 hours :(
 2017-02-17 19:35:08 +01:00
Wesley W. Terpstra 3931b0faff coreplex: assume L1 runs no slower than L2 2017-02-17 15:15:41 +01:00
Wesley W. Terpstra 5045696f92 TLRational: test all corners 
In order to ensure that verilator is happy, we launch both clocks from a
clock divider.  Sadly, it does not follow the spec wrt.  derived clocks.

See the verilator manual section on "Generated Clocks".
 2017-02-17 14:44:31 +01:00
Wesley W. Terpstra 91d1880dbf ClockDivider2: fix launch alignment of clocks (vcs) 
Doing this in Chisel leads to non-determinism due to shitty
Verilog ordering semantis. Using an '=' ensures that all of
the clock posedges fire before concurrent register updates.

See "Gotcha 29: Sequential logic that requires blocking assignments"
in "Verilog and SystemVerilog Gotchas" by Stuart Sutherland, Don Mills.
 2017-02-17 14:26:23 +01:00
Wesley W. Terpstra 924afebbd9 tilelink2: make TLRational have configurable direction 2017-02-17 13:59:54 +01:00
Wesley W. Terpstra bb334a2cf5 util: add fast2slow direction option to rational crossings 
If you manually specify which side of the crossing is slow, you
can move the registers fully to that clock domain.
 2017-02-17 13:59:51 +01:00
Wesley W. Terpstra e51609aec0 build: support waveform debug using opensource tools 
VCS is not free. Neither is the vcd format.
Fortunately, verilator and gtkwave ARE free ... and faster too.

This patch adds targets:
	run-regression-tests-fst
	run-asm-tests-fst
... which create opensource-compatible fst waveforms for gtkwave.
 2017-02-17 03:38:17 +01:00
Wesley W. TerpstraandGitHub abe344a1a4 tilelink2 Fuzzer: support read-only mode (#555) 2017-02-13 00:18:47 +01:00
Wesley W. TerpstraandGitHub 69f4c1a144 AddressDecoder: support AddressSets with infinite bits (#547) 2017-02-04 15:59:50 -08:00
Wesley W. TerpstraandGitHub 71f2445c62 Merge pull request #546 from ucb-bar/dev-zero 
Dev zero
 2017-02-03 19:49:56 -08:00
Wesley W. Terpstra d1744a5667 coreplex: zero memory channels is also allowed 2017-02-03 19:00:08 -08:00
Wesley W. Terpstra a3e56cfa5e rocketchip: add Zero device to the memory subsystem 2017-02-03 17:19:24 -08:00
Wesley W. Terpstra b240505a15 rocketchip: move memory channel Xbar from coreplex to rocketchip 
We want to keep the banks split in the outer SoC if there is an L3.
Furthermore, each channel might go to different memory subsystems,
like DDR/HMC/Zero, from rocketchip.
 2017-02-03 17:19:21 -08:00
Wesley W. Terpstra fc9ea62d38 HeterogeneousBag: a handy container for differently parameterized bundles 2017-02-03 16:21:33 -08:00
Wesley W. Terpstra 7afe383db3 Ecc: detect uncorrectable errors also for SEC 2017-02-03 16:21:09 -08:00
Wesley W. Terpstra 7aba066e67 tilelink2: add TLZero; /dev/zero suitable for putting behind locked cache ways 2017-02-03 16:20:27 -08:00
Wesley W. TerpstraandGitHub 93b2fa197e Artefact output (#545) 
* build: stop using empty .prm file

* generator: general-purpose mechanism for creating elaboration artefacts
 2017-02-02 19:24:55 -08:00
Wesley W. TerpstraandGitHub b2ee5e7d38 Merge pull request #540 from ucb-bar/dedup 
Dedup rocket
 2017-01-31 17:16:43 -08:00
Wesley W. Terpstra 9ca8f514c0 rocket: creating Bundles in an object also break dedup! 2017-01-31 14:45:11 -08:00
Wesley W. Terpstra e1577bb06e chisel3: bump chisel3 for work deduplication 2017-01-31 14:20:07 -08:00
Wesley W. Terpstra e5af59db68 rocketchip: work-around ucb-bar/chisel3#472 2017-01-31 14:20:02 -08:00
Wesley W. TerpstraandGitHub 9c0cc6fdf4 Merge pull request #537 from ucb-bar/l2-banks-together 
BankedL2Config: use the same LazyModule for all L2 banks
 2017-01-30 15:39:04 -08:00
Wesley W. Terpstra dc66c8857f diplomacy: be more robust using Java introspection 
If an error occures, some objects might only be partially initialized.
We want to still be able to get nice names for error messages.
 2017-01-30 14:25:12 -08:00
Wesley W. Terpstra 280af9684b BankedL2Config: use the same LazyModule for all L2 banks 
This makes it much easier for banked coherence managers to support
cross-bank functionality, like a common control port, for example.
 2017-01-30 14:02:59 -08:00
Wesley W. Terpstra f7f52cc722 diplomacy: restore Monitor functionality 2017-01-29 17:25:14 -08:00
Wesley W. Terpstra 972953868c uncore: switch to new diplomacy Node API 
Most adapters should work on multiple ports.
This patch changes them all.
 2017-01-29 15:54:45 -08:00
Wesley W. Terpstra 4d646939b0 diplomacy: make flexible-port adapters possible 2017-01-29 14:26:02 -08:00
Wesley W. Terpstra 24ee7f45f5 rocketchip: pass variable l1tol2 connections into coreplex 2017-01-29 11:18:36 -08:00
Wesley W. Terpstra d5fa159063 diplomacy: add :*= and :=* to support flexible # of edges 2017-01-28 21:32:36 -08:00
Wesley W. TerpstraandGitHub 03f2fe02ac coreplex: support rational crossing to L2 (#534) 2017-01-27 17:09:43 -08:00
Wesley W. TerpstraandGitHub 19c58630d2 Merge pull request #533 from ucb-bar/rational-crossing 
Rational clock crossing
 2017-01-26 22:30:04 -08:00
Wesley W. Terpstra 830d01329d RationalCrossing: add some documentation 2017-01-26 21:27:34 -08:00
Wesley W. Terpstra fc3b72084f tilelink2: add a rational clock crossing adapter 2017-01-26 20:07:28 -08:00
Wesley W. Terpstra 4b70386393 AsyncCrossing: disambiguate the file name 2017-01-26 20:07:28 -08:00
Wesley W. Terpstra 5cf4b0632d RationalCrossing: clock crossing between related clock domains 2017-01-26 20:07:28 -08:00
Wesley W. TerpstraandGitHub d1dedd25e7 Merge pull request #529 from ucb-bar/physical-optimization 
Physical optimization
 2017-01-24 18:59:07 -08:00
Wesley W. Terpstra 6ff35a387a tilelink2: disable A=>D bypass in ToAXI4 whenever possible 2017-01-24 18:11:00 -08:00
Wesley W. Terpstra 64e1de751d axi4: add a minLatency parameter 2017-01-24 18:11:00 -08:00
Wesley W. TerpstraandGitHub 46cdfc2b45 diplomacy: find names of LazyModules also in Seq() member values (#527) 2017-01-24 18:10:37 -08:00
Wesley W. TerpstraandHenry Cook 3fc55298ef coreplex: provide coherence managers with geometry information 2017-01-23 15:50:39 -08:00
Wesley W. TerpstraandHenry Cook d4b3a0f0be diplomacy: support given bits in AddressDecoder 2017-01-23 15:50:39 -08:00
Wesley W. TerpstraandHenry Cook c0b6d31377 tilelink2: Delayer adapter useful for unit tests 2017-01-23 15:50:39 -08:00
Wesley W. TerpstraandGitHub b3ef146805 Merge pull request #523 from ucb-bar/buffer-move 
coreplex: move TLBuffers for L2 and socBus
 2017-01-21 14:53:51 -08:00
Wesley W. Terpstra 38c9ddffcc BankedL2: move TLFilter BEFORE coherence manager 
This lets smart caches exclude the sets that are filtered.
 2017-01-21 13:23:07 -08:00
Wesley W. Terpstra dcadd5a006 coreplex: move TLBuffers for L2 and socBus 2017-01-20 22:23:36 -08:00
Wesley W. TerpstraandGitHub e8ce32a156 Merge pull request #515 from ucb-bar/cache-cork 
Cache cork
 2017-01-19 20:00:51 -08:00
Wesley W. Terpstra 9dc7f180b6 diplomacy: support zero-port Nodes 2017-01-19 19:08:01 -08:00
Wesley W. Terpstra c0496fab29 regression: disable build that times out on Travis 2017-01-19 19:07:59 -08:00
Wesley W. Terpstra 5d70265e86 rocket: L1 only needs cache-line transfer sizes 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra 3a5e5a65f8 coreplex: support multiple memory channels via diplomatic trickery 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra e7b35b4bb6 diplomacy: support multiple ports behind a BlindNode 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra 258abc5629 coreplex: re-enable stateless L2 config 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra 4bdb2e5d68 tilelink2 Monitor: ReleaseAck source does not count 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra fbf1073586 tilelink2: CacheCork - terminate caching 2017-01-19 19:07:14 -08:00
Wesley W. Terpstra bf7823f1c8 tilelink2: split suportsAcquire into T and B variants 2017-01-19 19:07:13 -08:00
Wesley W. TerpstraandHenry Cook 52bb6cd9d9 Configs: use a uniform syntax without Match exceptions (#507) 
* Configs: use a uniform syntax without Match exceptions

The old style of specifying Configs used total functions.  The only way to
indicate that a key was not matched was to throw an exception.  Not only was
this a performance concern, but it also caused confusing error messages
whenever you had a match failure from a lookup within a lookup.  The
exception could get handled by an outer-lookup that then reported the wrong
key as missing.
 2017-01-13 14:41:19 -08:00