riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao
33676e81f8 use isOneOf as much as possible 2016-08-19 09:56:06 -07:00
Howard Mao
d34e790ac0 get rid of duplicated code in rocket Util 2016-08-18 18:40:07 -07:00
Howard Mao
7671811ac9 merge uncore.Util into uncore.util 2016-08-18 18:33:46 -07:00
Colin Schmidt
0a6c05a5d8 connect top level interrupts to coreplex 2016-08-18 15:52:44 -07:00
Howard Mao
91a97d6773 add some more comments to describe the new device system 2016-08-18 15:06:55 -07:00
Howard Mao
1b6fa70b5c Add test for external TL clients (bus mastering) 2016-08-18 14:26:03 -07:00
Howard Mao
18982d7351 add default addrMapEntry definition which throws exception 2016-08-18 12:29:41 -07:00
Howard Mao
f7c42499bb allow ExtraDevices to have client ports as well as MMIO ports 2016-08-18 12:18:14 -07:00
Howard Mao
d771f37e7e rename BusPorts to ExternalClients 2016-08-18 10:54:24 -07:00
Howard Mao
10190197c3 allow coreplex to take in more than 1 bus port 2016-08-18 10:35:25 -07:00
David Biancolin
de316643d1 Merge pull request #205 from ucb-bar/configurable_memsize 
make memsize configurable
 2016-08-17 18:33:56 -07:00
David Biancolin
29600f64ec make memsize configurable 2016-08-17 16:31:34 -07:00
Andrew Waterman
5164f947c0 Validate mstatus.mpp/dcsr.prv values on MRET/DRET 
The registers can still hold invalid values, but an attempt to switch
to the mode stored therein will instead go to an implemented mode.
 2016-08-17 15:39:34 -07:00
Howard Mao
35fbbfc70d put test harness on the heap in emulator 2016-08-16 14:50:40 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel 
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
 2016-08-15 23:27:27 -07:00
Andrew Waterman
2d1d7266f5 Fix RV64 badaddr value on instruction faults with large addresses 
We were relying on ALU passthrough for this, but failed to override the
ALU dw argument, so bits above 31 could be discarded.
 2016-08-15 23:09:09 -07:00
Howard Mao
38e0967816 strip DMA and RoCC CSRs out of rocket and uncore (#201) 2016-08-15 23:08:55 -07:00
Howard Mao
47a0c880a4 make sure TLId set in Periphery 2016-08-15 13:58:23 -07:00
Howard Mao
e939af88aa explicitly set TLId for bus TL ports 2016-08-15 12:46:29 -07:00
Howard Mao
2c39f039b5 make external address map order overrideable 2016-08-15 11:40:28 -07:00
Howard Mao
fb476d193c refactor main App for better code re-use 2016-08-11 16:15:23 -07:00
Howard Mao
a756856d84 make sure coreplex sources included in make dependencies 2016-08-11 14:27:03 -07:00
Howard Mao
e0ae039235 fix config string generation for extra devices 2016-08-11 10:44:32 -07:00
Howard Mao
647dbefd9b split coreplex off into separate package 2016-08-10 18:04:22 -07:00
Howard Mao
163cba6a85 make sure all regressions actually run 2016-08-10 14:52:06 -07:00
Howard Mao
4bfa7ceb6a unit tests in Coreplex instead of Tile 2016-08-10 11:26:14 -07:00
Howard Mao
571d579b86 get unit tests working again 2016-08-10 11:23:07 -07:00
Howard Mao
0ee1ce4366 separate Coreplex and TopLevel parameter traits 2016-08-10 09:49:56 -07:00
Howard Mao
f95d319162 don't use secondary external address map; collapse submap instead 2016-08-09 22:29:38 -07:00
Howard Mao
2645f74af2 clean up addrmap flatten function 2016-08-09 22:14:32 -07:00
Howard Mao
33f13d5c49 don't repeat external addr map base 2016-08-09 21:20:54 -07:00
Howard Mao
3ea2f4a6c4 refactor top-level into coreplex and platform 2016-08-09 18:26:52 -07:00
Howard Mao
993da60f2c relax address map alignment requirement 2016-08-09 18:25:32 -07:00
Howard Mao
33d5905c50 don't synthesize vsim verilog in Travis 2016-08-09 18:24:59 -07:00
Howard Mao
405294167f fix TL -> Nasti converter w id 2016-08-09 18:24:23 -07:00
Andrew Waterman
2906c75167 Remove fsim, as it is the same as vsim, modulo CONFIG 2016-08-09 15:42:22 -07:00
Andrew Waterman
1b8f919db2 Remove unused CoreName parameter 2016-08-09 15:24:59 -07:00
Andrew Waterman
458520c8f6 Use a generic UInt for TileLink op sizes, rather than MT_xx enum 2016-08-09 15:24:51 -07:00
Andrew Waterman
a857b08c59 [rocket] compute D$ tag bits based upon # of arbiter ports 2016-08-09 14:40:48 -07:00
Howard Mao
2a5aeeae24 add sbt pack plugin (#197) 2016-08-08 19:31:03 -07:00
Howard Mao
dd1fed41b6 generate BootROM contents from assembly code 2016-08-05 16:39:21 -07:00
Palmer Dabbelt
dab96096b4 Add firrtl build dependencies 
Without this when I update firrtl the new version doesn't get built, so
my build is constantly failing.
 2016-08-05 14:45:00 -07:00
Howard Mao
9fa5b228b2 allow extra devices and top-level ports to be added without changing RocketChip.scala 2016-08-04 14:06:14 -07:00
Howard Mao
9c4e57aea5 example Rocc accelerator fixes 2016-08-04 11:17:13 -07:00
Howard Mao
410e3e5366 make sure TraceGen gets correct addresses 2016-08-04 11:08:25 -07:00
Howard Mao
0a85e92652 Allow additional internal MMIO devices to be created without changing BaseConfig 2016-08-04 11:04:52 -07:00
Andrew Waterman
cc0f8962fb [rocket] take physical memory attribute check off critical path 
Cache the attributes in the TLB instead.
 2016-08-02 17:21:03 -07:00
Andrew Waterman
76f33d88a6 [rocket] Respect physical memory protection during page table walks 2016-08-02 17:20:49 -07:00
Andrew Waterman
5d4f6383f2 [rocket] Automatically kill D$ access on address exceptions 
Doing this internally to the cache eliminates a long control path
from the cache to the core and back to the cache.
 2016-08-02 17:20:49 -07:00
Andrew Waterman
b54db0ba23 [rocket] don't update BTB on not-taken branches 
Only update the BHT; don't set the target prediction to pc+4.
 2016-08-02 17:20:49 -07:00