Henry Cook
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199e76fc77
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:31:27 -07:00 |
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Henry Cook
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de313d97de
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2013-08-02 16:30:09 -07:00 |
|
Henry Cook
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4eaab214d2
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
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Henry Cook
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bef6c1db35
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minor nbdcache cleanup
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2013-08-02 16:29:37 -07:00 |
|
Henry Cook
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bc2b45da12
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 14:55:06 -07:00 |
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Stephen Twigg
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c1b1a21a0f
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If +stats is set when running simv-debug, will only output vcd data when cr28 is high.
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2013-07-30 16:39:47 -07:00 |
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Stephen Twigg
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3132db4f90
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Add stats PCR (cr28) to be used to flag whether a core is doing 'interesting' activity.
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2013-07-30 16:36:28 -07:00 |
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Henry Cook
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4d916b56e3
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Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file.
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2013-07-24 23:28:43 -07:00 |
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Henry Cook
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d8440b042a
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Make compatible with scala 2.10. Refactor constants into package object. Remove networking primitives from package object. Clean up request generators. Chnage ++ to +: for appending to io.incoherent.
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2013-07-24 23:22:36 -07:00 |
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Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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Stephen Twigg
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3f874342a4
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Update chisel to appropriate version for reference chip build.
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2013-07-10 17:08:56 -07:00 |
|
Ben Keller
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c7bf1aaac9
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Merge branch 'master' of github.com:ucb-bar/reference-chip
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2013-07-10 16:01:25 -07:00 |
|
Ben Keller
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a72e0dc99e
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Updated riscv-tools reference
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2013-07-10 16:01:01 -07:00 |
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Henry Cook
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2796de01bf
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new tilelink arbiter types, reduced release xact trackers
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2013-07-09 15:41:27 -07:00 |
|
Henry Cook
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db8e5fda9b
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new tilelink arbiter types, reduced release xact trackers
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2013-07-09 15:37:42 -07:00 |
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Henry Cook
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5c00d0a030
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new tilelink arbiter type
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2013-07-09 15:31:46 -07:00 |
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Andrew Waterman
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c5f01f3f87
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update rocket
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2013-06-15 00:55:34 -07:00 |
|
Andrew Waterman
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7cc53c7725
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clean up Str
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2013-06-15 00:45:53 -07:00 |
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Andrew Waterman
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4ae0c68303
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require -std=c++11, as -std=c++0x doesn't cut it
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2013-06-14 00:28:42 -07:00 |
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Henry Cook
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896179cbb6
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removed bad mt test
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2013-06-14 00:14:18 -07:00 |
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Henry Cook
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85fbb650c9
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makefile support for new multithreading tests
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2013-06-13 15:34:54 -07:00 |
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Andrew Waterman
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ae0716fb6d
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Use chisel printf for logging
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2013-06-13 10:53:23 -07:00 |
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Andrew Waterman
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95c5147dc5
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Add RISC-V instruction disassembler
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2013-06-13 10:31:04 -07:00 |
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Stephen Twigg
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bd43ca8423
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Merge branch 'master' of github.com:ucb-bar/reference-chip
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2013-05-23 17:51:24 -07:00 |
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Henry Cook
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c06cbf523b
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Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore.
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2013-05-23 15:26:20 -07:00 |
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Henry Cook
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6a69d7d7b5
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pass closure to generate bank addr
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2013-05-23 14:58:19 -07:00 |
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Henry Cook
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9631b6081e
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Merge branch 'tilelink-data'
Conflicts:
src/package.scala
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2013-05-23 14:53:10 -07:00 |
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Henry Cook
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cf02f1ef01
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use new locking round robin arbiter
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2013-05-23 14:16:50 -07:00 |
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Henry Cook
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569d8fd796
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Merge branch 'tilelink-data'
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2013-05-23 14:14:40 -07:00 |
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Henry Cook
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12205b9684
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remove obsolete config file reader prototype
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2013-05-23 14:09:03 -07:00 |
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Andrew Waterman
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fe9adfe71b
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Simplify and correct integer multiplier
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2013-05-22 17:27:50 -07:00 |
|
Yunsup Lee
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26ed805862
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push chisel,riscv-rocket,uncore
linux kernel boots!
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2013-05-21 19:00:40 -07:00 |
|
Yunsup Lee
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11133d6d4c
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clock gate s2 registers in the frontend
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2013-05-21 18:59:21 -07:00 |
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Yunsup Lee
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c837c1d800
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fix bug in previous JALR commit
on commit tag 9a122c06d1bf11237d7fb0769d454a67bbb7400e
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2013-05-21 18:28:44 -07:00 |
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Henry Cook
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69b508ff39
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ported caches and htif to use new tilelink
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2013-05-21 17:21:04 -07:00 |
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Henry Cook
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4c1f105ce9
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added PairedData link type with matching crossbar, ported tilelink and uncore to use
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2013-05-21 17:19:07 -07:00 |
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Andrew Waterman
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28f914c3f2
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don't JALR to speculatively-bypassed addresses
Technically not necessary, but probably improves performance.
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2013-05-21 16:56:58 -07:00 |
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Yunsup Lee
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dcde377303
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Fix DM I$ deadlock
BTB predictions were causing infinite miss loops
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2013-05-20 15:22:58 -07:00 |
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Andrew Waterman
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3a1b5f01b2
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don't take interrupts while they're disabled!
a control bug allowed an interrupt to be taken on the instruction immediately
following an interrupt-disabling instruction (but not thereafter).
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2013-05-19 23:27:47 -07:00 |
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Andrew Waterman
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6eb4c2542a
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comment out I$ assert for now
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2013-05-18 18:09:23 -07:00 |
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Andrew Waterman
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1dab984231
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use UFix instead of Bits for arithmetic
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2013-05-18 00:45:29 -07:00 |
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Andrew Waterman
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dfa7a03f73
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use assert, not Assert
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2013-05-18 00:45:13 -07:00 |
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Yunsup Lee
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f3c78abc2b
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push riscv-tests
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2013-05-16 00:51:02 -07:00 |
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Yunsup Lee
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e77bde71d0
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push riscv-tools
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2013-05-15 12:03:52 -07:00 |
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Yunsup Lee
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f0b0867f5a
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push riscv-tests
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2013-05-13 19:22:28 -07:00 |
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Yunsup Lee
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f13605d2f5
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push riscv-tools
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2013-05-13 19:14:57 -07:00 |
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Yunsup Lee
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7ba3ab03e2
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update README
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2013-05-13 11:19:55 -07:00 |
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Yunsup Lee
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5b55cc93af
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add submodule riscv-tools
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2013-05-10 11:53:55 -07:00 |
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Andrew Waterman
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0672773c1a
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for now, don't use asserts outside of components
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2013-05-09 02:14:44 -07:00 |
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Andrew Waterman
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e8fcdb56a6
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update chisel to work around xilinx ise bug
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2013-05-03 01:47:15 -07:00 |
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