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Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
100 Commits 1 Branch 0 Tags 13 MiB
Scala 93.1%
C++ 2.1%
Python 2%
Makefile 1.2%
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Henry Cook c06cbf523b Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore.
2013-05-23 15:26:20 -07:00
chisel@2c93b2d07d Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore. 2013-05-23 15:26:20 -07:00
csrc add FPGA test bench 2013-05-02 04:59:32 -07:00
dramsim2@0b3ee6799a integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
emulator commit awesome vlsi/energy scripts 2013-05-01 02:59:11 -07:00
hardfloat@fc09bea899 upgrade to new rocket; improve vlsi makefiles 2012-11-17 07:21:29 -08:00
project print stack trace if elaboration fails 2012-11-20 05:39:48 -08:00
riscv-rocket@1b6244d6bf Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore. 2013-05-23 15:26:20 -07:00
riscv-tests@c4e3da6be3 push riscv-tests 2013-05-16 00:51:02 -07:00
riscv-tools@e3c80a865a push riscv-tools 2013-05-15 12:03:52 -07:00
src/main/scala Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore. 2013-05-23 15:26:20 -07:00
uncore@f238f04fd9 Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore. 2013-05-23 15:26:20 -07:00
.gitmodules add submodule riscv-tools 2013-05-10 11:53:55 -07:00
Makefrag commit awesome vlsi/energy scripts 2013-05-01 02:59:11 -07:00
README update README 2013-05-13 11:19:55 -07:00
sbt-launch.jar everything to get emulator working 2012-10-01 19:30:11 -07:00

README 

Quick and dirty instructions:

CHECKOUT THE CODE:

  git submodule update --init

  cd riscv-tools
  git submodule update --init


BUILDING THE TOOLCHAIN:

  To build RISC-V ISA simulator, frontend server, proxy kernel and newlib based GNU toolchain:

    export RISCV=/path/to/riscv/toolchain/installation
    cd riscv-tools
    ./build.sh

  To build asm tests and benchmarks (you must have the RISC-V toolchain installed and in your path):

    cd riscv-tests/isa/
    make -j

    cd riscv-tests/benchmarks
    make -j

BUILDING THE PROJECT:

  To build the C simulator:

    cd emulator
    make

  To build the VCS simulator:

    cd vlsi/build/vcs-sim-rtl
    make

  in either case, you can run a set of assembly tests or simple benchmarks:

    make run-asm-tests
    make run-vecasm-tests
    make run-vecasm-timer-tests
    make run-bmarks-test

  To build a C simulator that is capable of VCD waveform generation:

    cd emulator
    make emulator-debug

  And to run the assembly tests on the C simulator and generate waveforms:

    make run-asm-tests-debug
    make run-vecasm-tests-debug
    make run-vecasm-timer-tests-debug
    make run-bmarks-test-debug


UPDATING TO A NEWER VERSION OF CHISEL:

  To grab a newer version of chisel:

    git submodule update --init
    cd chisel
    git pull origin master

  Then, to compile it and install it into the rocket repo:

    cd sbt
    sbt package
    cp chisel/target/scala-2.8.1/chisel_2.8.1-1.1.jar ../../sbt/work/lib

  If you commit a new jar, you must also commit the updated chisel submodule.