acecc407a5
HellaCache: we do NOT really support probe below the block size!
...
If we did, you would somehow have to retain ownership of the
unprobed parts of the block, in case they happened to be dirty.
2018-02-15 19:08:43 -08:00
fe277cf6f0
Merge branch 'master' into auto-plusargs
2018-02-06 18:38:44 -08:00
efc6c9cbd3
Let user of CSRFile decide when to set tval
...
I also renamed badaddr to tval (the correct name).
2018-02-06 14:05:03 -08:00
a59fc3bdaa
Teach MulDiv to do either mul-only or div-only by setting unroll=0
2018-02-06 14:03:17 -08:00
69441930b5
Rationalize ALU function encoding
...
MULHSU and MULHU should match their ISA funct3 encodings to slightly
reduce HW cost.
2018-02-06 14:00:37 -08:00
5294523551
Keep io.cpu.s1_data for visibility ( #1218 )
2018-01-31 14:31:42 -08:00
f4853c4f63
Add cover properties to Core CSRs ( #1212 )
2018-01-30 00:01:19 -08:00
b5ff853e86
Sign-extend the depc CSR ( #1209 )
2018-01-26 12:07:33 -08:00
8d8e4e1399
Merge pull request #1196 from freechipsproject/interrupt-cover
...
Cover all exceptions and interrupts
2018-01-25 18:06:13 -08:00
d2399b6d0e
Cover all exceptions and interrupts
2018-01-25 16:14:56 -08:00
a2ca82f92c
Add VM covers
2018-01-23 16:13:35 -08:00
24c1235500
rocket: add address to tlb permissions require msgs
2018-01-18 10:31:51 -08:00
355d3b15e8
Merge 'origin/master' into auto-plusargs
2018-01-16 15:45:53 -05:00
80ca018e3a
Add cover points for BusErrorUnit ( #1193 )
2018-01-15 18:00:29 -08:00
e52d52ae99
Link PlusArg to emulator command line options
...
- adds a mutable singleton (PlusArgArtefacts) to store information
about Rocket PlusArgs
- adds methods to PlusArgArtefacts to emit C snippets that are
consumed by emulator.cc for correct argument parsing and help text
generation
- emits snippets in $(CONFIG).plusArgs via BaseCoreplex-set
ElaborationArtefacts
- modify emulator/Makefrag-verilator to include $(CONFIG).plusArgs
- cleanup help text (docstring) for existing PlusArgs
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 14:32:55 -05:00
f5211765e9
Merge pull request #1177 from freechipsproject/dont-touch-2
...
Make more use of chisel3.experimental.DontTouch
2018-01-09 15:13:55 -08:00
c152962642
Dual-port RAM replaced with single-port RAM for tag_array in HellaCache ( #1181 )
...
In accordance with https://github.com/freechipsproject/chisel3/issues/752
2018-01-09 13:06:43 -08:00
ad0b9a0b1b
Reduce cases in which FENCE.I must flush D$
...
Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.
2018-01-05 13:58:14 -08:00
4853d1355f
rocket: dontTouch HellaCache.io.cpu.resp
2018-01-05 12:50:24 -08:00
206892899f
Merge pull request #1171 from freechipsproject/fix-msb-check
...
Enforce physical-address canonicalization
2018-01-03 12:06:18 -08:00
ee1a9485df
Enforce physical-address canonicalization
...
When xLen > paddrBits, enforce that physical addresses are zero-extended.
This works by checking that the _virtual_ address is _sign_-extended, then
checking that its sign is positive.
2018-01-02 18:47:30 -08:00
7c9a1b0265
Correctly check for virtual-address canonicalization
...
The previous check was necessary but not sufficient.
2018-01-02 18:41:25 -08:00
b0e1bc3071
tile: cake reduction
...
* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
2018-01-02 17:49:08 -08:00
efe7165b54
tile: BaseTile refactor, pt 2
...
* 2 layer cake
* no more bundle traits, only call to IO
2018-01-02 15:37:31 -08:00
1cd018546c
tile: BaseTile refactor, pt 1
...
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
2017-12-26 11:04:15 -08:00
895c4b9261
Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) ( #1144 )" ( #1162 )
...
This reverts commit a542ae687e
2017-12-19 12:16:26 -08:00
09160d0cd5
Changed label for DCache and ICache error covers + take away exclusio… ( #1155 )
...
* Changed label for DCache and ICache error covers + take away exclusion that shouldn't be there
* rocket: add d-channel error to I$
2017-12-13 20:16:36 -08:00
a542ae687e
ICache: stores to the ITIM have effects (shrinking valid ITIM data) ( #1144 )
2017-12-08 17:35:14 -08:00
676110bc1f
Add cover for a1ebe6da4d
2017-12-07 21:03:42 -08:00
a1ebe6da4d
Prevent frontend deadlock fetching from uncacheable memory
...
After detecting a corrupted BTB, don't speculatively update it until
the next non-speculative fetch. This prevents the frontend from replaying
forever.
2017-12-07 18:56:06 -08:00
ec3789b365
Add Cross Cover Property Library ( #1149 )
...
Add cover points related to memory error to I/D Cache
2017-12-07 18:46:10 -08:00
5c204f98d5
When writing full words to ITIM, ECC errors are correctable ( #1148 )
...
* When writing full words to ITIM, ECC errors are correctable
* Disable D$ tag reset state machine when using scratchpad
2017-12-07 16:00:26 -08:00
50de991f18
Fix typo in breakpoint cover property.
2017-12-04 14:04:24 -08:00
71ddd797bf
Merge pull request #1138 from freechipsproject/cover_tag_ecc_error_during_fence_i
...
Added coverage point to cover the case when ECC error happens during …
2017-12-01 18:00:11 -08:00
7c2df9f0bf
Cover the case when there is an ECC error in DCache data array during fence.i execution
2017-12-01 16:28:28 -08:00
74bd61c556
Added coverage point to cover the case when ECC error happens during fence.i execution
2017-12-01 15:50:31 -08:00
a447343074
Merge pull request #1129 from freechipsproject/add-exception-cover-properties
...
Add cover properties for exceptions in the core.
2017-11-30 16:23:14 -08:00
4bd9c477ea
Add cover properties for ECALL exceptions.
2017-11-30 14:27:04 -08:00
29c70501f2
Add cover properties for exceptions in the core.
2017-11-30 14:27:04 -08:00
890528c641
Avoid data corruption under correctable tag error during flush
...
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable. Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
2017-11-29 16:09:44 -08:00
34d86ef665
Revert "Avoid data corruption under correctable tag error during flush ( #1130 )"
...
This reverts commit 44eb4d12b5
2017-11-29 16:09:30 -08:00
44eb4d12b5
Avoid data corruption under correctable tag error during flush ( #1130 )
...
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable. Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
2017-11-29 09:42:00 -08:00
5155eb6059
Don't emit writeback state machine logic for scratchpad ( #1127 )
...
Firrtl can't DCE it because it would require analyzing the state machine.
2017-11-22 18:40:02 -06:00
a60d7d419d
icache: add a couple cover points for I$ and ITIM iteraction
2017-11-20 13:14:38 -08:00
5e94884f09
Fix ITIM deallocation during I$ refill causing data corruption
...
Deallocation can change repl_way, which violates the assumption that it
remains constant throughout refill.
The workaround described in commit 3db066303b3db066303b
2017-11-20 12:30:40 -08:00
66b7a8a5ed
Revert "Fix ITIM bug overwriting I$ contents when deallocating ITIM ( #1079 )"
...
This reverts commit 3db066303b
2017-11-20 12:26:04 -08:00
f3575404c0
tile: bus blocker needs to know width :(
2017-11-17 20:17:17 -08:00
b625e68360
tile: put a BasicBusBlocker inside RocketTile ( #1115 )
...
...instead of on the master side of the system bus.
People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
2017-11-17 17:26:48 -08:00
7cfb69e2d5
Queue: silence some warnings
2017-11-14 15:09:09 -08:00
7098ebf439
rocket: fix itim GetPropertyByHartId ( #1109 )
...
needs to use RocketTileParams.hartid instead of zipWithIndex
2017-11-13 19:25:20 -08:00
Wesley W. Terpstra
Henry Cook
Andrew Waterman
solomatnikov
Jacob Chang
Andrew Waterman
Schuyler Eldridge
pentin-as
Richard Xia
Gleb Gagarin
Richard Xia
Yunsup Lee