riscv/rocket-chip
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217 Commits

Author SHA1 Message Date
Wesley W. Terpstra
72e5a97d40 tilelink2: factor out the OH1ToOH function 2016-10-16 22:04:01 -07:00
Wesley W. Terpstra
20288729b9 tilelink2 Isolation: cross the valid signals as well 
Refactor the code to be less copy-pasty
 2016-10-14 18:28:36 -07:00
Wesley W. Terpstra
ac0bb841da AsyncQueue: cope with far reset propagation delay 2016-10-14 18:05:35 -07:00
Wesley W. Terpstra
8f3c2ddfc3 tilelink2 Crossing: these asserts should be done by the AsyncQueue 2016-10-14 16:54:09 -07:00
Wesley W. Terpstra
a82cfb8306 tilelink2: replace addr_hi with address (#397) 
When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
 2016-10-14 14:09:39 -07:00
Wesley W. Terpstra
54b73aef57 tilelink2: WidthWidget and Fragmenter no longer erase latency 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
200cf3dd13 tilelink2 Nodes: include some options to test for conformance 2016-10-13 17:02:18 -07:00
Wesley W. Terpstra
5d5b5a66f4 tilelink2 RAMModel: fix a write-bad-data bug 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e5a1483358 tilelink2 Fragmenter: eliminate most of the registers on A 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
99c7003d11 tilelink2: allow preemption of Fragmenter and WidthWidget 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b42cfdc9dd tilelink2 Arbiter: there is only one winner 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
b6e9b0c558 tilelink2 Arbiter: allow preemption of first beat 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0aebf9e341 tilelink2 ToAXI4: no arbitration path register needed 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
0e897b905f tilelink2 RegisterRouter: data path register is no longer required 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
c4eadd3ab3 tilelink2 Monitor: enforce stricter transaction ordering 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
d8a1163131 tilelink2 Monitor: don't enforce Irrevocable any more 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
405f66da32 tilelink2 WidthWidget: cope with Decoupled inputs 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
e2e72ac979 tilelink2 Fragmenter: cope with Decoupled input 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
023c6402e9 tilelink2: switch to DecoupledIO syntax 2016-10-13 17:02:17 -07:00
Wesley W. Terpstra
a9a3f7dd4e tilelink2 RAMModel: include name of test in output 2016-10-12 17:08:52 -07:00
Wesley W. Terpstra
a423f97844 axi4: parameterized AXI master constraint for aligned access 2016-10-12 17:02:02 -07:00
Wesley W. Terpstra
673cf1fdb5 tilelink2 ToAXI4: must create irrevocable D for now 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
8e92ac32b7 tilelink2 ToAXI4: we need a Queue on B to guarantee deadlock freedom 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
38b6c1c820 tilelink2 axi4: RegisterRouter can cut ready dependency 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
dc26736f32 axi4 tilelink2: include minAlignment and maxAddress in slaves 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
538437384a tilelink2 Fragmenter: combine AccessAck errors 2016-10-12 17:02:01 -07:00
Wesley W. Terpstra
4caa543ad7 tilelink2: Fragmenter should not cut Acquire parameters 
The correct response to misuse is to fail a requirement check.
Pretending that things are not caches could lead to inconsistency.
 2016-10-11 22:38:03 -07:00
Wesley W. Terpstra
6336f94fa2 tilelink2: only caches can support B requests 2016-10-11 22:38:02 -07:00
Wesley W. Terpstra
4a975ca380 tilelink2: add a rightOR to go with our leftOR 2016-10-11 22:38:02 -07:00
Wesley W. Terpstra
b0e33f4a39 tilelink2: use TLArbiter in HintHandler 2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
683a2e6785 tilelink2: refactor firstlast helper method 2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
a404cd2abf tilelink2: use NodeHandle to restore Crossing.node API 2016-10-10 13:15:28 -07:00
Wesley W. Terpstra
876609eb0e diplomacy: add NodeHandles to support abstraction 2016-10-10 13:15:25 -07:00
Wesley W. Terpstra
97af07eb3e tilelink2: clarify use of Isolation 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
b5f5ef69c1 regmapper: eliminate race condition in RegisterCrossing bypass 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
f250426728 tilelink2: blow up if the channels carry data when they should not 2016-10-10 13:13:32 -07:00
Wesley W. Terpstra
6d6aa3eb13 tilelink2: Isolation must also connect reset_n 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
cb7b16f1a9 util: exchange resets between AsyncQueue source and sink 2016-10-10 13:13:31 -07:00
Wesley W. Terpstra
adf5f1807b tilelink2: ToAXI4 bridge added 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra
2f7081aeaf tilelink2: make mask generation reusable 2016-10-10 11:21:50 -07:00
Henry Cook
1e69a2dc1c [tilelink2] allow TL monitors to be globally enabled or disabled (#392) 2016-10-09 12:34:10 -07:00
Wesley W. Terpstra
e5ac0f717f tilelink2: split isolation gates by direction 2016-10-07 12:03:43 -07:00
Jacob Chang
fe641c14a1 tilelink2: Add support for different noise generator in fuzzer (#386) 2016-10-06 13:20:13 -07:00
Andrew Waterman
eddf1679f5 Use <> instead of := for bi-directional connections 2016-10-04 22:29:39 -07:00
Wesley W. Terpstra
6ec2e7c5bd tilelink2: Legacy should preserve the access size (#378) 
* tilelink2: Legacy should preserve the access size
* Legacy: extract missing size information for TL1 Puts
 2016-10-03 17:25:31 -07:00
Wesley W. Terpstra
f05298d9bc tilelink2: move general-purpose code out of tilelink2 package 2016-10-03 16:22:28 -07:00
Wesley W. Terpstra
c85e42a303 tilelink2: Nodes should accept full PortParameters 
We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
 2016-10-03 16:09:49 -07:00
Wesley W. Terpstra
f2ca2178bf graphML: CTO's like colour 2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
fe0875b084 LazyModule: output final verilog Module name 2016-10-03 15:05:45 -07:00
Wesley W. Terpstra
52c1a053ff tilelink2 RegisterRouter: test fully Decoupled behaviour 2016-10-02 02:24:02 -07:00